Figure
1-1
|
Transmitted data eye (left) and received data eye (right)
after two
connectors and 40 inches |
2 |
Figure
1-2
|
Transmitted
eye with pre-emphasis and received (right) eye |
8 |
Figure
1-3
|
Impulse
response and equalization |
8 |
Figure
1-4
|
Broadcom's
10Gbps data eye, using FR4 dielectric |
9 |
Figure
1-5
|
Conceptual
phase-locked loop |
10 |
Figure
2-1
|
HyperTransport configurations |
16 |
Figure
2-2
|
Interconnect examples using RapidIO |
19 |
Figure
2-3
|
RapidIO three-layer model |
20 |
Figure
2-4
|
PCI Express system connections |
24 |
Figure
2-5
|
Standard
line-card interfaces |
37 |
Figure
2-6
|
10G Ethernet physical
layer |
39 |
Figure
3-1
|
Transceivers in switch applications |
43 |
Figure
3-2
|
PCIe switches used to scale I/O in servers |
43 |
Figure
3-3
|
Display-interface receiver applications |
44 |
Figure
3-4
|
Chip-to-chip networking application |
45 |
Figure
3-5
|
Wireless baseband card using RapidIO switch chip |
46 |
Figure
4-1
|
Typical interconnect-bridge architecture |
48 |
Figure
4-2
|
HDMI receiver simplified block diagram |
50 |
Figure
5-1
|
Forecast for PCI Express bridge and switch chips, 2007–2011 |
59 |
Figure
5-2
|
Market share of PCIe bridge and switch chips in 2007 |
60 |
Figure
5-3
|
Revenue forecast for serial RapidIO switch chips, 2007–2011 |
61 |
Figure
6-1
|
IDT's RapidIO products in a simplified baseband card |
70 |
Figure
7-1
|
PLX PCI Express bridge |
81 |
Figure
10-1
|
Media gateway using the Tundra serial RapidIO switches |
96 |
Figure
10-2
|
Wireless baseband card |
96 |