| Figure 1-1. |
Firewalls and
the DMZ |
8 |
| Figure 2-1. |
Header and trailer
format for ESP tunnel mode |
21 |
| Figure 3-1. |
Block diagram of generic integrated security processor |
30 |
| Figure 3-2. |
Example of bit
permutation in the DES algorithm |
33 |
| Figure 3-3. |
Typical system
configuration with lookaside VPN/SSL processor |
34 |
| Figure 3-4. |
Typical curve
of IPSec performance versus packet size |
37 |
| Figure 4-1. |
Security-accelerator market forecast through 2011 |
48 |
| Figure 5-1. |
Cavium Octeon CN58xx block diagram |
53 |
| Figure 5-2. |
Integrated security appliance based on Cavium Octeon NSP |
54 |
| Figure 5-3. |
Freescale MPC8572 block diagram |
59 |
| Figure 5-4. |
Intel Tolapai block diagram |
64 |
| Figure 5-5. |
Netronome NFP3200 block diagram |
68 |
| Figure 5-6. |
Accelerator card based on Netronome NFP3200 |
69 |
| Figure 5-7. |
RMI XLR processor block diagram |
75 |
| Figure 5-8. |
Security appliance design based on RMI XLR |
76 |
| Figure 5-9. |
Tilera Tile64 block diagram |
79 |
| Figure 6-1. |
Security appliance using LSI T1000 |
88 |
| Figure 7-1. |
Broadcom BCM5825 block diagram |
98 |
| Figure 7-2. |
Cavium Nitrox II block diagram |
101 |
| Figure 7-3. |
Cavium Nitrox II IPSec flow-through system diagram |
102 |
| Figure 7-4. |
Hifn 8450 block diagram |
108 |
| Figure 7-5. |
SafeNet SafeXcel-184x block diagram |
113 |