Linley Spring Processor Conference 2018

April 11 - 12, 2018
Hyatt Regency, Santa Clara, CA

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Agenda for Day Two: April 12, 2018
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9:00am-10:00amKeynote

Big Data and Edge Processing Trends Point to RISC-V
Martin Fink, EVP and CTO, Western Digital

As Big Data applications emerge to enable autonomous driving, surveillance systems, and smart machines, they require special-purpose compute capabilities. These data-intensive workloads create opportunities for a new breed of purpose-built processors that will accelerate AI and machine learning both in the data center and at the edge of the network. RISC-V has the capabilities, foundation, ecosystem, and openness required for storage-centric architectures that support these applications. This presentation will discuss these trends and how they drove Western Digital to choose RISC-V to power its entire storage portfolio.

10:00am-10:30amSession 4: IoT Security

Nearly every week brings news of another IoT security breach that exposes users to identity theft or privacy loss. These breaches also expose companies to embarrassing publicity and potentially fatal liability. Effective security requires multiple layers – defense in depth. This session, moderated by The Linley Group senior analyst Tom Halfhill, describes IoT security technologies that start at the CPU cores and extend outward to the SoC platforms, operating systems, middleware, and application software.

Surviving the IoT Device Security Wild West
Suresh Marisetty, Principal Security Solutions Architect, Arm

Delivering on the promise of IoT requires trusted relationships between secure devices and services. Secure devices will bring confidence throughout the IoT value chain, enabling the vision of IoT scaling to trillions of connected devices. However, developing secure IoT devices often feels like surviving the 'wild west' due to inconsistent approaches and standards. The Arm Platform Security Architecture brings an industry-wide, common foundation, to establishing secure IoT devices--and their corresponding services — at scale.

10:30am-10:45amBREAK – Sponsored by Micron
10:45am-12:15pmSession 4: IoT Security (cont.)

Implementing Strong and Programmable Security to Mitigate IoT Threats
Steve Singer, Senior Director, WW Field Applications Engineering, Rambus

Securing an IoT device is daunting when third-party components such as OS and applications are exploited by attackers. Today, discrete security chips are commonly used to plug the security hole, but this approach has shortcomings as threats evolve. Alternatively, a programmable secure enclave residing within the main SoC can monitor the system in real-time for any security breaches. This presentation will discuss architectural tradeoffs for implementing a root of trust, along with provisioning a device identity for secure cloud communications.

Embedding Security Step by Step
Ron Keidar, Security Architect and Senior FAE, Inside Secure

Because their reputation and their success are at stake, service providers and device/auto makers must be confident that their applications execute as intended. They must be confident that their sensitive data cannot be extracted, modified, or intercepted, and their identity cannot be tampered with. This presentation will describe the process of securing connected devices with Inside Secure's Hardware Root-of-Trust solution.

Building End-to-End Security Into High-Value Embedded Applications
Rich Collins, Product Manager for ARC Processors, Synopsys

High-profile security breaches have become commonplace, even within embedded designs, yet many designers fail to implement security features in their SoCs due to lack of knowledge, along with perceived cost and complexity. Synopsys' end-to-end security subsystem solution combines critical hardware and software elements to reduce complexity and mitigate security-knowledge roadblocks. This complete solution protects against malware, device tampering, and exploitation of communication protocols targeting high-value applications such as integrated SIM, mobile payment, smart energy, and automotive telematics.

There will be Q&A and a panel discussion featuring above speakers.

12:15pm-1:30pmLUNCH – Sponsored by Arm
1:30pm-3:00pmSession 5: IoT Design

IoT devices span a wide range of applications from sensors to AR/VR headsets, but they generally have two basic requirements: efficient processing and wireless connectivity. This session, moderated by The Linley Group principal analyst Linley Gwennap, focuses IP cores and technologies to help processor vendors design SoCs for these IoT devices. It covers the newest CPU cores for embedded and IoT devices as well as IP for Bluetooth and Wi-Fi.

RISC-V Core IP: From Microcontrollers to Linux
Jack Kang, VP of Product and Business Development, SiFive

RISC-V has emerged as a compelling alternative to existing ISAs. Recent developments have seen RISC-V products announced for a wide variety of markets ranging from microcontrollers, to Linux application processors, all the way to vector computing for AI and machine learning. But what makes RISC-V so well suited for all of these markets? This presentation will provide an update on current silicon RISC-V devices, market opportunities for RISC-V adoption, upcoming plans for RISC-V, and what this all means for system designers and architects.

Turnkey Fully Integrated RISC-V–Based IP for Bluetooth and Wi-Fi
Sagi Zohar, Director of Customer Solution Group, CEVA

The success of IoT depends on the widespread adoption of industry standards such as Wi-Fi and Bluetooth wireless connectivity, enabling IoT devices to communicate seamlessly and safely with each other. Another key factor is the availability of a broad ecosystem providing software, tools, libraries, security means, and applications. The RISC-V ISA will create a new and open ecosystem that will boost the IoT market. The presentation will discuss CEVA's turnkey, fully integrated and optimized RISC-V-based Wi-Fi and Bluetooth IP platforms for embedding into SoCs and ASSPs.

Turning Augmented/Virtual Reality Hype Into Actual Reality
Amitabh Kumar, Director, Segment Marketing, GLOBALFOUNDRIES

This presentation will provide a semiconductor foundry's perspective on key semiconductor-related challenges, employing a holistic "electron in to photon out" system-level view to define the challenges. It will then propose solutions to help AR/VR to become a mainstream hardware product. The proposed solutions will cover several semiconductor areas including displays, sensors, processors, and connectivity.

There will be Q&A and a panel discussion featuring above speakers.

3:00pm-3:15pmBREAK – Sponsored by Micron
3:15pm-4:45pmSession 6: AI at the Edge

Deep-learning algorithms and neural-network processors are driving the rapid evolution of AI applications from data centers, to edge devices, and even to tiny low-power IoT-sensor nodes. This session, moderated by The Linley Group senior analyst Mike Demler, will describe deep-learning hardware and software frameworks that enable designers to build AI capabilities into low-power edge devices.

Seamless Prediction at the Edge Using TensorFlow on FPGAs
Brad Spiers, Principal Solutions Architect, Micron

IoT is exploding, with 50 billion sensors predicted by 2020. This large number of sensors creates daunting data streams. To businesses, though, the real value of IoT comes from learning what patterns lie hidden in these streams. At the edge, power constraints suggest using technologies like FPGAs. However, they have been notoriously difficult to program — until now. This presentation explains how to deploy deep-learning models created with TensorFlow — with no code change — on power-efficient Micron FPGA systems.

A Smart Interconnect Fabric for Enabling Embedded AI Applications
Anush Mohandass, Chief Operating Officer, NetSpeed Systems

From autonomous vehicles to autonomous kitchen appliances, AI solutions must deal with the real world. These chips must combine real-time processing with machine-learning accelerators running complex AI algorithms, which requires the implementation of high-performance heterogeneous architectures. This implies an architecture that must deal with real-time cache coherency between different processors running at different speeds and workloads. A smart interconnect fabric is a key enabling technology for next-generation AI systems and reducing the complexity of integrating heterogeneous architectures.

Scaling Up Imaging, Computer Vision, and AI DSP Performance
Lazaar Louis, Senior Director, Cadence

Smartphones, AR/VR headsets, smart home devices, surveillance cameras, automotive, drones and robots require high performance and power efficiency for imaging, speech processing, computer vision and on-device AI experiences. This presentation will share details on the performance and power efficiency improvements, and enhancements in processor pipeline, memory subsystem, data-management systems and software platform for Cadence IP cores. The software platform includes a Neural Network Compiler (XNNC) for enabling on-device AI inference using classification, segmentation and object-detection neural networks.

There will be Q&A and a panel discussion featuring above speakers.

4:45pmEND OF CONFERENCE

 

Premier Sponsor

Platinum Sponsor

Micron

Gold Sponsor

NetSpeed Systems

Industry Sponsor