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NXP Airs Software-Defined Radio

New QorIQ LA1575 Processor Has Programmable Baseband Engines

April 3, 2017

By Tom R. Halfhill


NXP’s first QorIQ LA-series chip has programmable baseband engines that can perform Layer 1 and Layer 2 network processing in software, so it’s adaptable to multiple communications standards. Along with its enhanced packet acceleration, the new LA1575 has enough horsepower to serve in multiple roles, including next-generation Wi-Fi routers, 5G cellular radios, and mixed wired/wireless applications, such as fixed-wireless nodes in neighborhood fiber-optic networks.

“LA” stands for Layerscape Access—a nod to the Layerscape chip architecture that Freescale (later acquired by NXP) introduced in 2012. The same architecture is the foundation of NXP’s existing LS1- and LS2-series processors (see MPR 7/9/12, “ARM Joins Hands With QorIQ”). All these products have 32- or 64-bit ARM cores.

Designed primarily for residential and small-business Internet gateways, enterprise access points, and fixed-wireless applications, the LA1575 will be available in dual- and quad-core variants. As Figure 1 shows, both models have ARM Cortex-A53 CPUs, and their target clock frequency is 1.4–1.6GHz. Although NXP is withholding many specifications for now, the most important new features are a programmable vector engine for Layer 1 processing, enhanced accelerators for Layer 2 processing, and an integrated RFIC interface with analog-to-digital and digital-to-analog converters (ADCs/DACs).

Figure 1. Block diagram of NXP’s QorIQ LA1575. Dotted lines indicate optional features. The new programmable vector engine, RFIC interface, and enhanced AIOP (advanced I/O processor) set this design apart from existing LS1-series chips.

The LA1575 doesn’t fit neatly into existing product categories. General-purpose embedded processors, including most other QorIQ products, require external chips to perform the physical-layer (PHY) and media-access-control (MAC) functions in Layer 1 and Layer 2, respectively. Wireless-base-station processors, including QorIQ Qonverge, integrate general-purpose CPUs with DSP cores to perform the cellular-baseband functions. The LA1575 integrates ARM CPUs with programmable baseband engines that support various wireless protocols, not just cellular.

Although this concept—known as software-defined radio—isn’t new, it’s unique in a product that otherwise is a general-purpose embedded processor. NXP says the LA1575 has enough performance to handle the IEEE 802.11ad and 802.11ax Wi-Fi standards as well as the millimeter-wave 5G cellular standards under development by the 3GPP. It is scheduled to begin sampling this month and begin volume production in early 2018.

LA1575 Gets Physical

In many respects, the LA1575 is similar to the LS1048A announced in 2015 (see MPR 7/13/15, “QorIQ Chips Add More ARMs”). Both have four Cortex-A53 CPUs, 10 Gigabit Ethernet (10GbE) ports, PCI Express (PCIe Gen3), Serial ATA (SATA3.0), SuperSpeed USB3.0, and cryptography acceleration. Both chips also implement the company’s second-generation Data Plane Acceleration Architecture (DPAA2) for packet processing. But the LS1048A, like other QorIQ embedded processors, requires external PHYs and modems for connections to wireless networks.

The LA1575’s new programmable vector engine enables NXP to implement the Layer 1 PHY modem in software, including forward error correction (FEC). It’s programmable for different basebands, and the company says it has tuned the instruction set during several iterations of cellular, Wi-Fi, and other wireless standards. This claim implies the engine isn’t entirely new but derives from an existing product.

A possible source is the Vector Signal Processing Accelerator (VSPA) in NXP’s Airfast AFD4400 digital-front-end (DFE) processor. Designed for the DFEs in small-cell base stations and remote radio units, the AFD4400 has 11 VSPA cores, each with its own single-instruction, multiple-data (SIMD) function units and floating-point hardware. The AFD4400 can execute 3.5Tflop/s. NXP may have adapted this field-proven DFE to the LA1575 and improved it to work with next-generation Wi-Fi and cellular standards, which are more demanding than existing standards.

The LA1575’s vector engine uses a 1,024-bit SIMD unit to execute up to 128 operations per clock cycle, and the chip has four of these engines. These vectors are much wider than ARM’s Neon SIMD extensions, which are limited to 128 bits. ARM recently announced the Scalable Vector Extensions (SVE) that support vectors up to 2,048 bits wide, but they are too new to appear in the LA1575 (see MPR 1/30/17, “ARM Chooses Variable-Length Vectors”). Wide vectors can deliver greater performance and power efficiency on parallel workloads than is possible by simply cranking up the clock speed.

Like Neon and Intel’s AVX, the LA1575’s SIMD instructions can perform either fixed- or floating-point operations. NXP says this flexibility enables developers to rapidly implement algorithms using popular tools such as Matlab. The company also provides special development tools for the vector engine, including a C compiler and a signal-processing library optimized for communications. In addition, it will offer PHY/MAC firmware, packet-acceleration firmware, and an optimized Linux OpenWRT stack.

Firmware In the Works

NXP hopes to receive Wi-Fi Alliance (WFA) certification for 802.11ac Wave 2 in 3Q17. Next on the roadmap is 802.11ax certification, probably by the end of this year, followed by 802.11ad. The early-access development kit already supports multiuser MIMO (MU-MIMO) and modulation coding up to QAM-1,024 for 802.11ax.

The company is also developing a 5G-cellular software stack that derives from a demo system shown at Mobile World Congress. Because the LA1575’s PHY and MAC layers are programmable, it hopes to achieve 3GPP certification without modifying any hardware, tweaking the software as needed to ensure compliance and interoperability. Because the 3GPP is still working on it, the 5G standard remains in flux; the specifications should be firm next year, and early commercial deployments may begin in 2019 (see MPR 3/10/17, “March Modem Madness”).

As Figure 2 shows, customers can integrate NXP’s firmware with their own software. Alternatively, they can program the hardware directly using NXP’s CodeWarrior integrated development environment (IDE), which is based on the popular open-source Eclipse IDE. The company has introduced a new LA1575 development board (“Rio”) that supports 4x4 and 8x8 MIMO for Wi-Fi. 

Figure 2. NXP’s LA1575 software. The company offers almost all the software required for a typical Wi-Fi network stack, with some components available from third parties.

In addition to the vector engine, the LA1575 has an enhanced version of the advanced I/O processor (AIOP)—a vital part of the company’s DPAA2 packet-acceleration hardware. The 20Gbps AIOP is a coprocessor complex likely based on 32-bit Power Architecture cores previously designed by Freescale. It, too, is therefore programmable in C using standard development tools. Several QorIQ LS1 and LS2 processors implement DPAA2 and the AIOP (see MPR 7/20/15, “Freescale Overhauls the Data Plane”).

In the LA1575, however, the AIOP can now fully offload the MAC protocols for Layer 2 processing—both the latency-sensitive MAC processing and the higher-level bridging. Previous AIOP implementations lacked this capability.

Thus, the new vector engine and the AIOP work together to perform both the Layer 1 and Layer 2 processing on chip, enabling developers to use the LA1575 for cellular, Wi-Fi, or wireline networking simply by changing the firmware—assuming the firmware is available or the customer can write it. In conventional designs, external chips typically handle this processing. By offloading these functions, the Cortex-A53 CPUs are free to run other tasks, such as customer applications, control-plane software, and virtual network functions (VNFs).

Qualcomm Is Coming

So far, we have yet to see any competing embedded processors integrate the same programmable baseband features for next-generation Wi-Fi and cellular communications. Several companies have enough relevant technology to design similar chips, probably with some help from third-party intellectual property. For now, though, their embedded products rely on external hardware to perform the Layer 1 and Layer 2 functions that the LA1575 can execute on chip.

Qualcomm is closest to duplicating the LA1575 but takes a different approach. The new IPQ8074 integrates 2.4GHz and 5.0GHz Wi-Fi radios on an SoC that, like NXP’s chip, has quad Cortex-A53 CPUs for control-plane chores (see MPR 2/27/17, “Qualcomm Bids for 802.11ax”). Likewise, the IPQ8074 has two proprietary accelerators for data-plane processing and similar I/O interfaces, including 10GbE and PCIe (Gen2, not Gen3). And as with NXP’s chip, the IPQ8074 supports 8x8 MIMO, MU-MIMO, and QAM-1,024 coding for 802.11ax. Qualcomm is withholding most other details, but the vital difference is the integrated Wi-Fi. The LA1575 lacks those radios but integrates the PHY/MAC processing and an RFIC interface for external radios.

Integrated solutions aren’t always cheaper or more power efficient than discrete solutions, however. For now, NXP and Qualcomm are declining to reveal the volume pricing and power consumption for their new products, so we can’t make useful comparisons. All things being equal, the additional hardware will increase the chip’s power as well as cost. And some things are not equal: instead of moving to the 16nm FinFET+ process at TSMC, NXP is manufacturing the LA1575 in the same 28nm CMOS technology that QorIQ LS chips employ, whereas Qualcomm is manufacturing the IPQ8074 in 14nm FinFET. Extrapolating from other QorIQ chips, we estimate the LA1575 will consume about 15W (typical) to 20W (maximum) and sell for about $90 in volume. We estimate the IPQ8074 will cost less.

Keep in mind that Qualcomm is currently in the process of acquiring NXP. If it completes the acquisition this year as expected, the merged company will look for redundancies in the respective product lines. The QorIQ family has more history and popularity than the IPQ family, but no QorIQ processor integrates a radio like the IPQ8074 does. On the other hand, no IPQ processor integrates a programmable PHY/MAC like the LA1575 does. Despite their common Cortex-A53 CPUs, software compatibility is superficial—their software stacks are specific to their proprietary engines, so these chips are largely incompatible below the operating system.

Better Integration Than the Competition

Table 1 compares the LA1575 with two other processors that have similar features except for the programmable PHY/MAC hardware: Broadcom’s StrataGX BCM58713 (code-named Northstar2) and Cavium’s Octeon TX CN8030 (see MPR 5/16/16, “Broadcom Offers First 64-Bit StrataGX,” and MPR 5/16/16, “Octeon Expands Market With ARM”).

 

Table 1. Comparison of three embedded processors for communications. Note that the Broadcom and Cavium offerings require external PHY and MAC chips for connections to wireless networks. (Source: vendors, except *The Linley Group estimate)

The BCM58713 provides more CPU horsepower by using Cortex-A57 instead of Cortex-A53, but it lacks the signal-processing strength of the LA1575’s new vector engine. ARM’s 128-bit Neon SIMD is no match for NXP’s 1,024-bit SIMD. The BCM58713 does, however, integrate Broadcom’s FlexSparx v2 engine, which uses two Cortex-R7 cores and additional hardware to accelerate cryptography and packet processing. The Broadcom specifications for IPSec processing and Layer 3 forwarding are in the same range as our estimates for the NXP chip. Although NXP is withholding details about the I/O interfaces, they are probably similar to those in the BCM58713.

Cavium’s custom ARMv8-compatible ThunderX CPUs are weaker than the A53 and A57 CPUs in the other two chips. To compensate, Octeon has always included powerful accelerators. For example, the CN8030’s Nitrox V crypto engine is adapted from Cavium’s discrete Nitrox security processors. The CN8030 also implements the virtual-NIC (vNIC) technology that first appeared in the higher-end ThunderX server processors. The vNIC supports hypervisors with Single Root I/O Virtualization (SR-IOV) and has larger packet queues and buffers than previous Octeon III chips. Cavium also increased the packet performance by enhancing its TCP offload engine to perform LRO (large-receive offload) and LSO (large-send offload). The company says TCP scatter/gather operations (which combine TCP segments) are twice as fast as in Octeon III.

The biggest difference between the LA1575 and these competitors is its integrated MAC/PHY. To compensate, designers must combine the Broadcom or Cavium processors with an appropriate baseband chip, such as a Wi-Fi controller or a cellular modem. These external wireless chips add cost, power, and board area to the design. Depending on the choice of protocol and supplier, the wireless chip could close the gap in cost and power between the LA1575 and its competitors.

Better comparisons can follow when NXP discloses more information about its new product. Its standout features are the programmable PHY and MAC accelerators, which bring new capabilities to the QorIQ family. They allow a single chip to handle the Layer 1 and Layer 2 processing for Wi-Fi or cellular links—using today’s standards or tomorrow’s. Indeed, NXP suggests the LA1575 can handle both types of wireless links simultaneously. In this case, competitors would require two external wireless chips, likely tilting the comparison in NXP’s favor.

Hardware Versus Software

Thus, the ideal LA1575 application would use its internal capabilities to simultaneously provide Wi-Fi and cellular service. One example is a fixed-wireless gateway, which could be deployed as part of a fiber-to-the-neighborhood buildout that uses fixed wireless to avoid running fiber to each home. The gateway would access the short-range cellular signal to provide Internet service to Wi-Fi devices in a home or small business. The programmable basebands would enable field upgrades as new standards evolve.

Another opportunity might be in wireless backhaul. In areas where broadband wireline service is unavailable or uneconomical, some base stations use a microwave uplink. The LA1575 could be programmed for both the cellular connection to the client and the microwave protocol. This design, however, would require a full cellular protocol stack (2G/3G/4G/5G) that is certified with multiple operators as well as proprietary backhaul firmware.

Historically, the disadvantage of software-defined radio is that dedicated hardware, when manufactured in high volumes, can usually do the job more efficiently in cost and power. Initial deployments may use a programmable design, but dedicated chips become more economical when the standards solidify and volumes ramp. This trend is particularly true for massively deployed standards such as cellular and Wi-Fi, which rapidly attract optimized products. Programmable radios often find a niche in lower-volume wireless applications, such as industrial and military networks. NXP says it designed the LA1575 to be competitive against high-volume dedicated products, but it has not disclosed enough information to validate this claim.

The chip’s architects began this project before NXP accepted Qualcomm’s acquisition bid. Much has changed since then. The merger will add tremendous wireless expertise to the mix, and Qualcomm may prefer to rely on its own proven cellular and Wi-Fi technology while leveraging NXP’s embedded processor and SoC expertise. In the meantime, the LA1575 is an innovative offering that can expand the QorIQ family’s reach in communications infrastructure.

Price and Availability

NXP’s QorIQ LA1575 is scheduled to sample in April 2017 and begin volume production six to nine months later. The company is withholding pricing until production nears, but we estimate the chip will cost about $90 in 1,000-unit volumes. For more information, access www.nxp.com/LA1575. For more information about NXP’s Airfast AFD4400, from which the vector engine likely derives, access www.nxp.com/AFD4400.

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