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Linley Newsletter   Analysis of microprocessor and semiconductor developments

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Arteris Upgrades NoC for AI
The new version of Arteris IP’s network-on-a-chip (NoC) intellectual property adds several upgrades, including features that help to design artificial-intelligence processors and other SoCs.
Imagination Cuts GNSS Power
A new package of synthesizable intellectual property (IP) for integrating a low-power global-navigation receiver in SoCs, the Ensigma Series 4 takes “snapshots” to save energy when determining location.
Intel, AMD Monsters Battle for HPC
SC18 brought new server-processor disclosures from Intel and AMD. The former announced its 48-core Cascade Lake Advanced Performance while the latter disclosed new details of its 64-core Rome. 
SiFive Raises RISC-V Performance
At the Linley Fall Processor Conference, SiFive revealed its 7 Series cores. The new CPU is its most complex yet, moving into the same class as Arm’s “little” Cortex-A family.
Wave Exposes Broad Roadmap
Wave Computing is offering evaluation versions of its initial AI-acceleration systems while developing a second-generation ASIC, new MIPS cores, and its first licensable AI accelerators.
AIware3 Adds Rings to Neural Engine
AImotive’s third-generation licensable engine for autonomous-vehicle neural networks employs a new configurable ring structure that can connect multiple compute units to boost performance.
Cadence HiFi 5 Is a Smart Listener
The new licensable DSP handles speech recognition in digital assistants and other devices with voice interfaces. Relative to HiFi 4, it doubles audio-DSP performance and quadruples inference-engine performance.
Flex Logix Spins Neural Accelerator
Known for its embedded-FPGA IP, the startup is developing the NMax inference engine, a licensable core that scales from 512GMAC/s to 74TMAC/s or more.
LS1028A Targets Cars and Factories
NXP’s Layerscape LS1028A adds IEEE 802.1 Time-Sensitive Networking (TSN) and a graphics unit to its Ethernet controllers for mission-critical industrial and automotive applications.
PowerVR Halves GPU-Memory Needs
Imagination’s new PVRIC4 compression guarantees bandwidth savings of at least 50%, enabling designers to optimize their memory subsystem.
Eta Compute MCU Puts AI in IoT
The startup’s new Tensai chip combines an MCU with a DSP for machine learning. Eta completes its solution with optimized neural-network software for machine learning.
Tachyum Tries for Hyperscale Servers
The startup is developing a 64-core server processor, targeting tapeout late next year. The 7nm design implements a VLIW instruction set with custom vector and matrix instructions and a custom fabric.
Arm Frees FPGAs to Use Cortex-M
Arm is enabling free use of certain Cortex-M CPUs in Xilinx FPGAs, even for volume production. The new DesignStart FPGA program offers Cortex-M1 and Cortex-M3.
IBM Power9 Scales Up in Servers
IBM’s Power9 processor for scale-up servers, now available on the merchant market, employs external memory buffers to offer leading bandwidth and capacity, plus up to 16-socket configurations.
Intel 9th Generation Adds Little
Intel’s newest processors for gamers and content creators, Basin Falls and Coffee Lake-S Refresh, jump to eight cores in the Core i9-9900K but offer few other upgrades over the previous generation.
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Linley Fall Processor Conference 2018
Covers processors and IP cores used in embedded, communications, automotive, IoT, and server designs.
October 31 - November 1, 2018
Hyatt Regency, Santa Clara, CA
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