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Dual-Issue ARC Boosts Performance

June 13, 2017

Author: Mike Demler

Synopsys has announced a new DesignWare ARC HS family of licensable CPU cores for high-performance low-power embedded applications. The new design enhances the architecture by adding dual-issue capability to the 10-stage ARC HS pipeline. The HS4x CPUs run the same software as previous HS models, but they deliver a 25% boost in CoreMarks per megahertz compared with the ARC HS3x. Designers can alternatively use the new architecture to deliver the same performance at a lower frequency than the previous version, reducing power consumption.

The new dual-issue capability modestly increases die area (to 0.25mm2 for the HS48 versus 0.21mm2 for the HS38) but improves both areal and power efficiency. For the fully configured ARC HS48, performance per square millimeter increases by 14% and performance per milliwatt increases by 29%. The MetaWare compiler automatically optimizes instruction execution to take advantage of the dual-issue scheduler, so the HS4x is a drop-in replacement for its predecessor and is transparent to the programmer.

Along with the new base HS4x configurations, Synopsys also developed a new ARC HS4xD processor core that adds DSP extensions previously available only with ARC EM. The ARCv2-DSP ISA adds more than 150 signal-processing instructions for audio, speech, and wireless-baseband applications. RTL for the new cores is available now, and the company plans to deliver the ARC HS4x/4xD for general release in September. We expect the first production parts using the new cores to arrive in 4Q18.

Subscribers can view the full article in the Microprocessor Report.

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