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Intel Bridges Gap to 2.5D Packaging

June 20, 2017

Author: David Kanter

Although Intel is most famous for its silicon manufacturing, it also has formidable expertise in high-performance packaging. As CMOS scaling has become more complicated, the company has turned to advanced packaging and heterogeneous integration to increase performance. For example, the Xeon Phi 7200 (née Knights Landing) was one of the first processors to use copackaged high-speed memory in the data center.

Intel’s proprietary Embedded Multi-Die Interconnect Bridge (EMIB) is a further step in this direction. EMIB is a novel 2.5D packaging technology for creating high-bandwidth connections; it shifts the complexity away from logic fabrication and toward the packaging. This tradeoff is feasible because Intel controls both wafer fabrication and packaging.

Rather than using a large silicon interposer, as most 2.5D packaging does, EMIB forms connections through small bridge chips that are embedded in the package substrate beneath the active die. Eliminating the interposer makes Intel’s multi-die assembly more complicated but less expensive and more scalable. In particular, chips that connect using EMIB can fill the entire package, whereas interposers are constrained by conventional lithography. The first product to use EMIB was an FPGA, but Intel will likely soon apply the technique to high-performance server processors and may later apply it to mainstream notebook and desktop processors.

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