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Cortus APS3V Plays the RISC-V Card

June 27, 2017

Author: Loyd Case

RISC-V keeps rolling on, with Cortus becoming the third vendor of CPU intellectual property (IP) to adopt the open architecture. The company modified its APS23 CPU by replacing the instruction set with RISC-V, creating the new APS3V. To accommodate that ISA, the APS3V implements a longer pipeline and expanded register set. Production RTL is available now.

RISC-V is general-purpose ISA that’s BSD licensed, extensible, and royalty free. In addition, several RISC-V CPUs are available as open-source RTL. Most were developed at universities—including UC Berkeley, where the architecture first emerged. Cortus joins SiFive and Andes Technology in offering commercial RISC-V cores. Unlike the Andes NX25, which customizes the instruction set, the APS3V implements the basic ISA. Cortus is a platinum founding member of the RISC-V Foundation.

To simplify its development effort, Cortus began with the APS23. It reworked the instruction decoder in its configuration tools to implement the RISC-V RV32I ISA. The company also expanded the register file from 16 to 32 entries to accommodate the RISC-V standard. It implemented RISC-V code compression to reduce code size, a feature that’s important to embedded designers.

The new CPU expands the pipeline from three stages in the APS23 to as many as seven—a necessary change to hit the higher target frequency and simplify synthesis. The company claims the APS3V can operate as fast as 2.2GHz in 28nm HKMG, more than twice the speed of the previous design. Customers can select a five-stage design without external-memory access, or they can select a seven-stage design. Cortus reused other aspects of the APS23, including the cache.

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