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Achronix Turns to Embedded FPGAs

July 18, 2017

Author: Loring Wirbel

Achronix launched its first Speedcore embedded-FPGA intellectual property (IP) in 2016 and anticipates launching Speedchip FPGA “chiplets” for 2.5D packages next year. This strategy places the company’s high-performance Speedster FPGAs in a supporting role. It also reflects more than just changing customer needs: Achronix recognizes that direct competition with Xilinx and Intel could prove impossible. Although Intel is the foundry for the newest Speedster line, it has been an Achronix competitor since its 2015 purchase of Altera.

The Speedcore embedded FPGA (eFPGA) offers three types of expandable IP blocks along with customer-defined mixes of reconfigurable logic blocks (RLBs), block-RAM elements, and 64-bit DSPs. An RLB includes four quad-input lookup tables (LUTs), flip-flops, and a 4-bit ALU. Each DSP block has an 18x27-bit multiplier, a 64-bit accumulator, and a 27-bit pre-adder. Achronix refrains from defining I/O blocks, as it intends the IP to be wholly embedded in a customer’s ASIC. It offers the Achronix CAD Environment (Ace) design tools, which integrate with standard electronic-design-automation (EDA) environments. But like an ASIC vendor, it provides back-end verification services.

The company’s most immediate competition could come from Flex Logix and other embedded-IP specialists, but its challenge is in effectively moving away from catalog FPGA devices. The company says its annual revenue will exceed $100 million for the first time in 2017, and design starts for the new Speedcore are showing considerable growth. These designs initially employed 50k to 150k LUTs, but some recent ones have 10k to 20k. Although the first customers were OEMs, Achronix is seeing interest from chip companies wishing to embed Speedcore in their ASSPs.

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