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Andes Dual Issues New CPU Cores

August 8, 2017

Author: Loyd Case

Andes Technology continues to release CPU intellectual property (IP) at a rapid clip. Its new superscalar AndesCore N15 delivers a twist on dual-issue CPU architecture, and its RISC-V portfolio now includes the 32-bit N25. The N15 RTL is available for licensing, and the N25 RTL is slated to arrive in 3Q17. Andes launched the two new IP cores at the recent Linley IoT Hardware Conference.

The N15 is the company’s most powerful CPU core and its first superscalar design. It implements an asymmetric dual-issue pipeline with six stages, and it offers a DSP option. The design includes dynamic branch prediction and an optional memory-management unit (MMU), enabling it to boot a full Linux OS. The company positions the N15 as the successor to the N10, a single-issue CPU with a five-stage pipeline and an optional DSP. It aims the N10 at more-sophisticated IoT applications that require DSP and floating-point support, such as voice-enabled speakers. The N15 delivers higher performance than the older N10 at the expense of greater power.

Yet the N15 may be the final hurrah for the AndeStar V3 instruction-set architecture (ISA), as the company is looking to RISC-V for future cores. The N25 closely resembles the NX25, replacing the 64-bit elements of the latter CPU with a RISC-V RV32IMAC–compliant 32-bit microcore. In addition to the basic RISC-V ISA, the Andes cores implement proprietary extensions to improve performance and simplify the transition from the company’s original ISA. Thus, code compiled for RV32 will run on the N25, but code that takes full advantage of the Andes design won’t run on generic RISC-V cores. The company calls this extended RISC-V version its AndeStar v5 ISA. The new core implements AndeStar V5m, a 32-bit version more suitable for MCUs.

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