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Centriq Is the King of Cache

October 10, 2017

Author: Tom R. Halfhill

Qualcomm disclosed more details about its Centriq 2400 server processor at the recent Linley Processor Conference, confirming it’s one of the most powerful ARMv8 designs yet. The 48-core chip, which has been sampling for nearly a year, resembles Cavium’s future 54-core ThunderX2 in many respects but falls short of the best x86 server chips. Even so, it’s an impressive initial effort for a new server-processor vendor to target cloud-service providers.

The Centriq 2400 has 48 of the new 64-bit Falkor CPUs arranged in pairs that share an L2 cache. At the conference, Qualcomm revealed that each L2 cache is 512KB, for a total of 12MB. In addition, the L3 cache comprises twelve 5MB partitions distributed around the internal ring network that connects all the CPUs, caches, memory controllers, I/O interfaces, and other elements. Effectively, the L3 cache is 60MB, so the total L2/L3 cache is 72MB—or 26% more than Intel’s top-end Xeon Scalable server chip.

The company disclosed a few more details about the on-chip ring network. This bidirectional ring enables full coherence among all the CPUs, caches, and I/O controllers. To achieve the target bandwidth of 280GB/s, the ring is actually divided into four 512-bit-wide rings, two in each direction. Ring traffic is divided into 128-byte blocks, matching the size of the L2 and L3 cache lines. The odd and even packets are interleaved across the two parallel rings. Reads are multicast to reduce traffic where possible.

Compared with the first-generation designs from other ARM vendors, the Centriq 2400 is better in several respects, including core count, cache size, and memory bandwidth. It has some innovative (if unproven) features for compressing DRAM bandwidth and optimizing the L3 cache. It’s the first server processor to boldly abandon 32-bit software compatibility, and it’s debuting in a 10nm FinFET process.

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