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IC Economics Limit Performance

March 27, 2018

Author: Linley Gwennap

Remember when transistors were free? In the heyday of Moore’s Law, chip designers counted on each new process node to double their transistor budget. More recently, that bounty faded as rising wafer-processing complexity all but eliminated transistor-cost gains. Designers must therefore scale back their next-generation designs to fit the cost constraints of their target markets. This trend is already slowing progress in processor performance and features, especially in cost-focused markets.

PCs are a good example. In a mature market with price pressure from end customers, Intel has hunkered down for the past several years, continuing to offer quad-core processors with modest CPU-architecture improvements. Last year, Coffee Lake bucked the trend with a six-core configuration, but even including that design, we estimate Intel’s relative die area (normalized for process technology) is rising less than 10% per year, causing the actual die area to decrease over time. A similar trend appears in midrange smartphone processors, which have been stuck at eight Cortex-A53 CPUs for the past few years.

For companies lucky enough to have high-margin products or customers desperate to pay for performance increases, the right strategy is still to stay on the leading-edge node and cram more and more transistors into their designs. High-end smartphone processors, for example, have been among the first products to jump to new process nodes. Similarly, Nvidia and Intel continue to pack more cores into their high-end data-center products. But most chip vendors are more judicious in adding new transistor-hungry features. One result of this slower growth is an ongoing decline in die sizes.

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