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MIPS I7200 CPU Dons New Threads

May 15, 2018

Author: Mike Demler

The new MIPS I7200 is a licensable 32-bit CPU optimized for multithreaded real-time control in LTE-Advanced and 5G modems. It’s also suited to handling the control plane in Wi-Fi router and gateway chips. The company developed the I7200 in partnership with MediaTek, one of several modem-chip vendors that use MIPS CPUs, along with Altair (Sony), Qualcomm Atheros, and Sequans. RTL is available now for general licensing.

The I7200 is the first new MIPS core since Imagination spun off the company late last year to Tallwood Venture Capital. It offers upgrades to the 32-bit interAptiv CPU, which the company introduced in 2012. Compared with its predecessor, the I7200 delivers a 50% boost in dual-thread performance, but it consumes 20% more die area.

For the new design, the company also focused on increasing code density. The I7200 implements a new ISA, called nanoMIPS, that supports variable-length 16-, 32-, and 48-bit instructions. Whereas MIPS previously implemented 16-bit instructions in the MIPS16e2 extension to the base ISA, it includes such commands in nanoMIPS.

The company tested the new ISA using the CSiBe code-size benchmark, developed by the University of Szeged (Hungary), for the GCC compiler. On those tests, nanoMIPS compresses by approximately 15% programs that contain the most frequently used MIPS16e2 instructions. Performance-optimized MIPS32 code receives a 35% reduction.

Subscribers can view the full article in the Microprocessor Report.

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