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eSilicon 7nm Serdes Hits 56Gbps

July 17, 2018

Author: Mike Demler

ASIC provider eSilicon specializes in high-performance devices for communications infrastructure, networking, and other data-center applications. Using 7nm TSMC technology, it has developed ASIC-design platforms under the NeuASIC brand. Each includes hard and soft macros for networking applications along with a new architecture and intellectual-property (IP) library for building AI accelerators.

The NeuASIC platforms give designers a variety of power-optimized memory compilers, serdes, and 2.5D-IC interposers. The 7nm library includes a 56Gbps serdes, High Bandwidth Memory 2 (HBM2) PHY, and ternary-content-addressable-memory (TCAM) compiler, as well as networking-optimized I/Os and other components.

In 2017, after Marvell shut down most of its European operations, eSilicon acquired the Italian engineering team that had developed a 56Gbps Marvell serdes for manufacture in 28nm technology. That group used the same ADC/DSP-based architecture to develop a 7nm serdes, which now appears in the NeuASIC platforms and is available separately as a licensable core. This new serdes enables PAM4 and NRZ coding, and its programmability allows designers to tune power/performance for long or short channels.

To maximize memory bandwidth, the company manufactures networking products in 2.5D packages using silicon interposers to combine the ASIC die with stacked DRAM chips. For AI accelerators, NeuASIC will enable designers to integrate a custom deep-learning accelerator (DLA) in an ASIC chassis comprising a CPU, scratchpad RAM, and HBM2 interfaces.

Subscribers can view the full article in the Microprocessor Report.

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