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Intel to Offer Structured ASICs

August 14, 2018

Author: Linley Gwennap

Intel’s pending acquisition of eASIC shines a light on structured ASICs, a niche technology in the vast ASIC market. Intel sees the move as complementary to both its large FPGA business (formerly Altera) and its custom-ASIC business (formerly part of LSI). The company plans to invest in the new business to move its structured ASICs to the next process node and add new hard cores to the platform. It declined to reveal how much it paid for eASIC, saying the price is immaterial to earnings.

Structured ASICs are similar to FPGAs in providing a pool of logic cells, memory cells, and I/O drivers that can be connected to create a variety of designs. Whereas customers configure an FPGA dynamically at run time, they configure a structured ASIC by modifying a single layer of the chip design. This approach eliminates much of the overhead of an FPGA, locking in cost and power savings. Although customers must create the structured-ASIC design before manufacturing, the design process is much simpler than for a custom ASIC. Thus, the structured ASIC provides an intermediate step between an FPGA and a custom ASIC.

Structured ASICs (also called gate-array ASICs) have existed for decades. Several ASIC vendors, such as Fujitsu, LSI Logic, and NEC, once offered them, but all exited the market by 2007. Altera used a similar technology as part of its FPGA-conversion program called HardCopy, but it eventually discontinued this program as customer interest dwindled. Toshiba continues to offer a similar customizable product it calls FFSA, with but modest success. The other vendor that has persevered with this technology is eASIC. We estimate the privately held company’s annual revenue at less than $100 million, representing considerably less than 1% of the total ASIC market.

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