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Xilinx Versal Surpasses UltraScale+

October 9, 2018

Author: Tom R. Halfhill

Xilinx plans to tape out its next-generation chips this quarter and begin sampling to major customers in mid-2019 using 7nm TSMC FinFET technology. At the recent Xilinx Developer Forum, the company also replaced the Everest code-name with the official brand: Versal, a portmanteau of “versatile” and “universal.” Xilinx rejects the FPGA label in favor of a new generic moniker: adaptive compute acceleration platform (ACAP). Although we doubt other vendors will adopt that name, we agree these devices are full-fledged SoCs containing programmable logic, not just FPGAs with some SoC elements.

Every Versal chip will have dual Arm Cortex-A72 application CPUs and dual Cortex-R5 real-time CPUs with floating-point units. Today, only the Zynq family integrates Arm cores, and they’re less powerful Cortex-A53s and Cortex-R5s without FPUs. The Versal chips also have a new network-on-a-chip (NoC) that tightly binds all the processing elements, local memories, and I/O interfaces. Some Versal products will include the new software-programmable accelerators described at Hot Chips in August. Now, the company is calling them AI Engines—a marketing reference to their features for artificial-intelligence processing.

Although the company has announced Versal products in only two tiers—the AI Core Series and Prime Series—eventually it’ll offer four others. AI Edge is for edge applications, including automotive, and AI Core is for data centers. Future AI RF chips will add the analog logic that first appeared in the Zynq UltraScale+ RFSoC family last year. The other three Versal tiers—Prime, Premium, and HBM—lack AI Engines but have faster serdes, more network interfaces, and cryptography acceleration. The HBM tier will copackage High Bandwidth Memory, as some Virtex FPGAs do. And some future models will have more programmable logic than the initial ones. 

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