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Arm Frees FPGAs to Use Cortex-M

October 23, 2018

Author: Bob Wheeler

Striking back against RISC-V, Arm is enabling free use of certain Cortex-M CPUs in Xilinx FPGAs, even for volume production. The new DesignStart FPGA program offers Cortex-M1, an FPGA-optimized version of Cortex-M0, and the general-purpose Cortex-M3. Given that some Xilinx UltraScale+ models integrate Cortex-A53 and Cortex-R5 hard cores, the new M1/M3 cores will serve primarily in lower-cost 28nm Spartan-7 and Artix-7 designs. They can run an RTOS for real-time control functions or serve embedded management functions.

Introduced in 2006, Cortex-M1 is a simple CPU designed for microcontrollers and conforms with the Arm v6-M instruction set, which is a subset of v7-M. To minimize logic-cell use, it employs the FPGA’s multiplier blocks—part of the DSP slice—for ALUs and other functions. Another mature design (dating to 2004), Cortex-M3 is the precursor to the newer Cortex-M4 and Cortex-M33. It implements the Arm v7-M ISA. Arm plans to release the Xilinx-targeted M3 at the end of October, at which time further details will be available. It intends Cortex-M1 for simple control and management functions, whereas the M3 can serve as the main CPU in various embedded and IoT applications.

Arm says the existing DesignStart programs have led to more than 3,000 downloads and 300 commercial licenses in the last 12 months. DesignStart FPGA lowers the barrier further by removing royalties, helping it protect its ISA against encroachment by RISC-V. Because most existing customers will want newer designs like Cortex-M33 and Cortex-A55, the company can afford to use dated cores to combat RISC-V’s growing developer mindshare.

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