Editor: Linley
Gwennap In This Issue
A Guide to Ethernet Switch and PHY Chips is now available, providing up-to-date coverage of Gigabit and 10G Ethernet switch and PHY chips as well as an overview of the emerging market for Power over Ethernet. For more information, visit our web site. Dune Launches New Fabric and MACs This week, Dune Networks announced several new switch-fabric products in its Petra family. The P130 can aggregate eight 10GbE ports into a single SPAUI or XAUI interface. The carrier-grade device supports ingress and egress DRAM buffers as well as programmable parsing and classification. Dune also rolled out new FAP (fabric access processor) and FE (fabric element) devices that increase the capacity of Dune's fabric and provide standard Ethernet interfaces. Designed for line cards, the FAP provides fabric access and traffic management. The FAP can be configured in a mesh connecting to other FAPs or it can be connected to a central fabric switch (the FE). The FAP P220 and P230 extend the density of FAP devices to 40Gbps and 80Gbps, respectively. The chips' line interfaces can be configured at rates of 1Gbps, 3.125Gbps, or 6.25Gbps to support XAUI, SPAUI, RXAUI, or SGMII. The backplane interface operates at the new 6.25Gbps rate for the newest FE or at 3.125Gbps for backward compatibility with previous FAP and FE devices. For improved performance, the new FAP chips use external DRAM memory to buffer data. The new FE 600 integrates serdes at 6.25Gbps to support 96 FAP devices in a single-stage configuration. Using external data buffers and dynamic routing in the fabric, Dune's fabric can implement multistage configurations with very high bandwidth. On the basis of its nonblocking performance, integration, and scalability, Dune's fabric continues to be the best in its class. Using the new FAP devices, this fabric can scale to hundreds of terabytes in bandwidth. The new XAUI and SGMII interfaces simplify the use of Dune's fabric for Ethernet applications. Overall, this is a good solution for OEMs seeking a highly scalable 10Gbps fabric or OEMs looking to maximize performance. --Jag Complete coverage of these products appears in our new report A Guide to Ethernet Switch and PHY Chips.
After abandoning the high-density voice market several years ago, Broadcom this week reentered that market with the BCM6515 voice processor. Performing complex voice coding for up to 72 lines, the processor targets access equipment such as multiservice access platforms, where voice ports operate in parallel with DSL ports. The BCM6515 uses Broadcom's own "Firepath" DSP, which also appears in its DSL processors and is available with several codecs. In 2000, Broadcom acquired startup Silicon Spice and later released its Calisto chip, a VoIP processor capable of handling a similar number of channels, as the BCM1510. Despite winning several designs for this chip, Broadcom de-emphasized Calisto because the market for Class-5 and Class-4 replacement switches failed to develop. Recent changes have motivated Broadcom to reenter this market. DSL penetration has grown significantly in the past eight years. At the same time, DSLAMs have migrated from ATM-based designs to Ethernet/IP-based designs, and DSLAM deployments are moving from high-density central-office installations to lower-density remote installations. Meanwhile, the economics of IP-based transport of voice have improved. Thus, it makes sense for equipment makers to create IP-based platforms supporting both voice and DSL and for chip suppliers to create VoIP processors supporting channel densities similar to DSL port densities (but no greater). At the same time, it does not make sense for Broadcom to develop one DSP for voice and another for DSL when a single core can serve both markets. The new VoIP chip will be marketed by the same group that already supplies the other major ICs for IP DSLAMs: the DSL transceiver, a companion NPU, Ethernet serdes, and Ethernet switches. Thus, the BCM6515 rounds out Broadcom's chip set for multiservice access platforms (MSAP). --Joe Our upcoming Linley Tech seminar on November 5 will include presentations on VoIP and MSAP design. This week, Broadcom released high-level details on its new VDSL2 residential-gateway processor. The BCM6368 integrates a VDSL2/ADSl2+ transceiver with analog front end, a MIPS CPU, an ATM or packet SAR, a four-port Fast Ethernet switch with PHYs, and dual USB interfaces. Combined with the company's software, the processor supports VoIP channels, encryption and decryption, and wire-speed bridging between Ethernet and VDSL2. Although Broadcom is late to this market, it still has a chance to win significant designs. Broadcom announced design wins at Chunghwa Telecom (CHT) - where we believe it displaced Ikanos, because of the latter's schedule delays. --Jag Additional coverage of Broadcom's VDSL2 products appears in our report A Guide to Broadband Chips. Morgan Kaufmann has released a new textbook, "Network Processors: Architecture, Programming, and Implementation," that provides a comprehensive discussion of packet processing. Written by Professor Ran Giladi of Israel's Ben-Gurion University, the book includes hardware and software design examples based on the EZchip NPU architecture. Readers can even download microcode development tools and test their own code. Professor Giladi uses his industry experience to create real-world examples, giving his readers the background they need to design and program NPU-based systems. --Linley Additional coverage of network processors appears in our report A Guide to Network Processors.
The Linley Tech seminar on November 5 will feature a packed lineup of technical presentations addressing two key themes: high-speed embedded processors and specialized processors for CPE and access applications. The presentations will address processor architecture and design and their applications in networking and communications. Presentations will include:
Don't miss the opportunity to hear these distinguished technical speakers discussing the newest processors and design trends. This Linley Tech seminar will be held in San Jose at the DoubleTree Hotel. Mark your calendars and register now at our web site. Free admission for qualified attendees is made possible by our event sponsors: Freescale, AMCC, LSI, Ikanos, Octasic, Marvell, Sun Microsystems, and Cavium Networks
We recently completed a white paper describing the lengthy effort behind Marvell's recent launch of the Sheeva processor line. We examine these new processors and their applicability to communications, printers, storage, consumer, and mobile applications, and provide a peek at some next-generation CPUs. Click here to download the white paper.
On October 21, Jag Bolaria, senior analyst with The Linley Group, will moderate a panel on the Ethernet Ecosystem at the AdvancedTCA Summit at the Santa Clara Convention Center. The panel will explore how Ethernet fits into AdvancedTCA and MicroTCA applications. For more information, visit the conference web site.
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