| Order a report

A Guide to CPU Cores and Processor IP
Focusing on CPU, GPU, and NoC IP

Sixth Edition

Published December 2015

Authors: Mike Demler and Loyd Case

Single License: $4,495 (single copy, one user)
Corporate License: $5,995

Ordering Information



Everyone Needs IP

With rising transistor budgets and the trend toward system-on-a-chip design, designing an entire complex ASIC or ASSP in house has become increasingly impractical. As a result, the market for licensed function blocks, known as intellectual property (IP), is growing rapidly. The most popular IP blocks are programmable processors such as CPUs and GPUs. As system designers seek simpler ways to connect all of their IP cores, we have seen surging interest in network-on-a-chip (NoC) IP as well.

Several suppliers provide CPU IP, each offering unique advantages. Some CPUs are easily customized, others are superscalar, while still others support multiprocessor implementations. GPUs can accelerate 2D, 3D, and/or vector graphics using fixed or programmable engines. NoC IP provides a scalable and configurable interconnect to reduce the design burden. For all types of IP, the available options range widely in performance, die area, and power.

"A Guide to CPU Cores and Processor IP" sorts through these options, evaluating the high-performance designs available from the leading IP vendors. The report provides in-depth coverage of CPUs and GPUs, including those from ARM, Cadence (Tensilica), Imagination (MIPS), Synopsys (ARC), and Vivante. Also covered are Adapteva, Aeroflex Gaisler, Andes, Beyond Semiconductor, and Cortus, as well as NoC IP vendors Arteris, NetSpeed, and Sonics.

Make the Right Choice

For each vendor, we describe each IP core offered, provide key metrics such as performance and die area, discuss important topics such as development tools and support, outline the future roadmap, and summarize the strengths and weaknesses of the offering. The report also provides background on how IP is used, an overview of common end markets such as consumer electronics and networking equipment, and market share and forecast data for the types of IP covered. We conclude with a side-by-side comparison of IP cores and our long-term views on the industry.

As the leading vendor of technology analysis for mobile and communications chips, The Linley Group has the expertise to deliver a comprehensive look at this burgeoning market. Analysts Mike Demler and Loyd Case use their extensive experience in the semiconductor market to deliver the technical and strategic information you need to make informed business decisions.

Whether you are looking for an innovative solution for your design, a vendor to partner with, or a rising company to invest in, this report will cut your research time and save you money. Get the inside scoop on this major market. Order "A Guide to CPU Cores and Processor IP" today.

This report is written for:

  • Engineers who need to select IP for the ASICs or standard products (ASSPs) they are designing
  • Marketing and engineering staff at companies that sell IP, design services, or software that runs on processor IP
  • Technology professionals who want an introduction to CPU, GPU, or NoC IP
  • Financial analysts who desire a detailed analysis and comparison of IP companies and their chances of success
  • Press and public relations professionals who need to get up to speed on IP technology

What's New in this Edition

Updates to the Sixth Edition of "A Guide to CPU Cores and Processor IP"

"A Guide to CPU Cores and Processor IP" has been updated to incorporate new announcements made since the publication of the previous edition.

Here are some of the many changes you will find:

  • Added coverage of ARM Cortex-A72, Cortex-A35, ARMv8-M, and updated ARM roadmap
  • Added coverage of Mali 470 GPU for wearables
  • Added coverage of Imagination (MIPS) M6200 and M6250 and the high-performance P6600 64-bit CPU.
  • Added coverage of Imagination Technology’s G6020 GPU for IoT
  • Added coverage of Synopsys ARC SecureShield
  • Added coverage of Vivante’s pending acquisition by VeriSilicon
  • New coverage of Soft Machines and its novel CPU IP
  • New coverage of NoC IP from Arteris, NetSpeed, and Sonics
  • New coverage of ARM CCI and CCN connectivity IP
  • All new comparisons for CPUs, GPUs, and NoCs
  • 2014 and preliminary 2015 market-size and vendor-share data
  • Updated market forecast through 2019

The processor-IP market continues to grow as more SoC designers adopt licensed cores for CPUs, GPUs, and NoCs. More than 19 billion chips containing CPU IP shipped during 2015. Despite slowing growth in the smartphone and tablet markets, CPU-IP shipments surged 23% in 2015, compared with 16% in 2014. An increase in the number of CPU-IP chips per smartphone boosted these shipments. We expect CPU IP to maintain a 12% compound annual growth rate (CAGR) through 2019 as the mobile market continues to mature and microcontroller growth slows.

The slowdown in smartphone shipments and decline in tablet sales negatively affected most GPU-IP vendors in 2015. After growing 23% in 2014, the number of chips using GPU IP rose just 6% in 2015, reaching 1.29 billion units. These numbers exclude chips using in-house GPU designs, such as Qualcomm’s and Nvidia’s. The growth rate for GPU-IP shipments lags that of CPU IP as the cycle of replacing basic phones with smartphones nears its conclusion.

Cellular handsets continue to be the highest-volume market for CPU and GPU IP. A single handset may have separate CPUs for the cellular baseband, application subsystem, and peripheral functions such as Bluetooth, GPS, Wi-Fi, touchscreen, and power management. Other important IP markets include chips for digital TVs, Blu-ray players, tablet computers, and set-top boxes; processors for personal media players; processors for home networking gear such as broadband gateways and Wi-Fi routers; storage controllers for hard drives and flash-memory drives; and processors for communications infrastructure and data-center servers.

Because of their growing complexity, most of these systems use ever more and faster CPUs. Except where performance concerns outweigh those of power, cost, and size, these CPUs are integrated into a larger-scale chip. Chip designers face a make-versus-buy decision for CPUs; most choose to buy (license) an IP core and focus their efforts on combining IP blocks, peripherals, and custom logic into a design that’s ideal for their end application.

This report covers an emerging IP type: network-on-a-chip. NoCs address the problem of increasing complexity in modern SoCs, providing an automated method of linking all the cores together. Unlike CPU and GPU cores, NoC IP must be heavily customized for each SoC, requiring a more tools-based approach. Compared with designing interconnects by hand, this approach reduces design time and helps optimize power.

ARM is by far the leading CPU-IP supplier, having a 79% share in 2015. Although its CPU cores serve in nearly every handset, its fastest-growing product line is Cortex-M for microcontrollers. ARM’s designs range from low-end CPUs such as Cortex-M0+ to high-performance superscalar designs such as the 64-bit Cortex-A72. Its Mali, the best-selling GPU IP, is particularly popular in low-cost smartphones.

Imagination Technologies has been supplying GPU IP since the 1990s, and it remains the leader in high-performance graphics units. Its Series7 GPU delivers industry-leading performance in Apple’s iPad Pro. Vivante, a startup with area-efficient GPUs, lost its leading customer when Marvell exited the smartphone market; it recently agreed to be acquired by VeriSilicon.

Synopsys has expanded its DesignWare library to include configurable ARC cores and complete subsystems, such as SoundWave for audio. In 2015, the company added new DSP capabilities to its ARC lineup. Including its considerable success in flash controllers, ARC appeared in 1.85 billion chips in 2015, ranking second in CPU-IP units.

After acquiring MIPS in 2013, Imagination completely refreshed its CPU lineup. The company’s new 64-bit P6600 offers a more area-efficient alternative to Cortex-A72 at the high end of the market, and its midrange I6400 has a unique multithreading capability that boosts performance.

Taking a different tack, Cadence provides an innovative customizable processor architecture called Xtensa, as well as preconfigured designs. The former Tensilica architecture competes for designs requiring a CPU, high-performance DSP, audio processor, video engine, or baseband-processing DSP. In 2015, Xtensa posted the highest growth rate among the four major CPU-IP architectures.

A number of smaller CPU-IP vendors — such as Andes, Beyond Semiconductor, and Cortus — offer alternatives to customers for whom compatibility with a more well-known instruction set is less important than small die size and low licensing fees. These cores are often deeply embedded in wireless chips, networking subsystems, and IoT devices. Combined, these vendors saw 2015 shipments of more than 600 million chips using their IP.

Sonics is the largest independent developer of NoC IP, offering the broadest range of NoCs, including subsidiary products for memory control and power management. Arteris complements its basic NoC features with support for fault-tolerant networks and a timing-closure tool. NetSpeed focuses on automating the entire NoC process, and it is the only one of these three to enable cache coherence. ARM’s connectivity IP is widely used for clusters of CPUs, but the company lacks a comprehensive and automated solution, leaving the door open for independent NoC vendors.

Different designers emphasize different parameters for the IP they use, such as interfaces, available I/O bandwidth, power consumption, die area, performance, instruction-set compatibility, and roadmap. Therefore, selecting the right IP is a complex and difficult task. This report details each vendor’s products, strategy, and market position, with a focus on high-performance CPU, GPU, and NoC IP.

List of Figures
List of Tables
About the Authors
About the Publisher
Preface
Executive Summary
1 Semiconductor-IP Overview
What Is IP?
Delivering and Instantiating IP
Soft Cores Versus Hard Cores
Process Technology and Libraries
Applications of IP
Cellular Handsets
Other Mobile Applications
Consumer Applications
Networking and Storage Applications
Microcontrollers, Smartcards, and Other Applications
2 IP Technology
IP Standards
Accellera and IP-XACT
Verilog and VHDL RTL/HDL Standards
Synthesis and Place and Route
Amba and OCP
Multimedia Standards
Video Resolution and Frame Rates
Audio Codecs
Video Codecs
Digital-Rights Management
Graphics Standards
2D Graphics
3D Graphics
3D-Graphics Pipeline
3D-Shader Architecture
Graphics Performance
Cellular Technologies
2G Technologies
3G Technologies
3.5G Technologies
4G Technologies
3 IP Implementations
What Is a CPU?
What Is Not a CPU
What Is a GPU?
What Is Not a GPU
Processor Microarchitecture
Data Types
Instruction Issue
Pipelining and Penalties
Caches and Tightly Coupled Memory (TCM)
Multicore and SMP
Multithreading
CPU Design
MMUs and TLBs
Hardware Virtualization
GPU Design
Unified Shaders
Tile-Based Deferred Rendering
Preliminary Z Testing
Typical GPU Architecture
NoC Design
Bus Matrix
Crossbar
Network-on-a-Chip
Benchmarks
CPU Benchmarks
Graphics Benchmarks
4 Market Size and Trends
Market Size and Share
CPU IP
GPU IP
IP Application Markets
IP Shipments by Application Category
Application-Market Trends
Processor-IP Forecast
CPU-IP Forecast
GPU-IP Forecast
IP Trends
5 ARM
Company Background
ARM Instruction Set
Key Features and Performance
32-Bit Cortex-A CPUs
64-Bit Cortex-A CPUs
Cortex-R CPUs
Cortex-M CPUs
Mali GPUs
Design Details
Big.Little
Neon
Cortex-A15
Cortex-A17
Cortex-A7
Cortex-A57
Cortex-A72
Cortex-A53
Cortex-A35
Cortex-R CPUs
Cortex-M CPUs
Mali Graphics Processors
Development Tools
Product Roadmap
Conclusions
6 Andes
Company Background
AndeStar Instruction Set
Key Features and Performance
Design Details
Development Tools
Product Roadmap
Conclusions
7 Cadence (Tensilica)
Company Background
Xtensa Instruction Set
Key Features and Performance
Design Details
Development Tools
Product Roadmap
Conclusions
8 Imagination (MIPS)
Company Background
MIPS Instruction Set
Key Features and Performance
Warrior CPUs
PowerVR GPUs
Design Details
M-Class CPU
P-Class CPU
I-Class CPU
PowerVR Series7 GPU
Development Tools
Product Roadmap
Conclusions
9 Synopsys (ARC)
Company Background
ARC Instruction Set
Key Features and Performance
Design Details
Development Tools
Product Roadmap
Conclusions
10 Vivante
Company Background
Key Features and Performance
Design Details
Development Tools
Product Roadmap
Conclusions
11 Other IP Suppliers
Adapteva
Company Background
Key Features and Performance
Conclusions
Beyond Semiconductor
Company Background
Key Features and Performance
Conclusions
Cobham Gaisler
Company Background
Key Features and Performance
Conclusions
Cortus
Company Background
Key Features and Performance
Conclusions
Soft Machines
Company Background
Key Features and Performance
Conclusions
12 Interconnect IP
ARM
Company Background
Key Features and Performance
Conclusions
Arteris
Company Background
Key Features and Performance
Conclusions
NetSpeed
Company Background
Key Features and Performance
Conclusions
Sonics
Company Background
Key Features and Performance
Conclusions
Comparing Interconnect IP
Automation
Coherence
Product Breadth
Conclusions
13 Comparing Processor IP
CPU Cores
Low-End Embedded CPUs
Midrange Embedded CPUs
High-End Embedded CPUs
High-Performance Application CPUs
GPU Cores
GPUs for Wearables
Low-Cost GPUs
Midrange GPUs
High-End GPUs
14 Conclusions
Market and Technology Directions
System Trends
CPU-IP Trends
GPU-IP Trends
NoC-IP Trends
Vendor Outlook
ARM
Imagination
Synopsys
Cadence
Andes
Other Vendors
Closing Thoughts
Appendix: Further Reading
Index
Figure 1‑1. Block diagram of a generic basic phone.
Figure 1‑2. Block diagram of a generic application processor.
Figure 1‑3. Block diagram of a generic mobile Wi-Fi chip.
Figure 1‑4. Block diagram of a generic digital-TV chip.
Figure 1‑5. Block diagram of a generic 802.11 access point.
Figure 1‑6. Block diagram of a generic premium hard-drive controller.
Figure 2‑1. Logic circuit that implements simple Verilog code.
Figure 2‑2. GDS II file being edited in Magic.
Figure 2‑3. Raster graphics versus vector graphics.
Figure 2‑4. Apple’s Cover Flow effect.
Figure 2‑5. Standard hard-wired 3D pipeline.
Figure 2‑6. Standard programmable 3D pipeline.
Figure 3‑1. CPU pipelining examples.
Figure 3‑2. Generic multicore processor.
Figure 3‑3. Interleaved tasks on a multithreaded processor.
Figure 3‑4. Block diagram of a generic CPU.
Figure 3‑5. Block diagram of a generic shader-based 3D GPU.
Figure 3‑6. Block diagram of a bus matrix.
Figure 3‑7. Block diagram of a generic NoC.
Figure 4‑1. Unit market share for 32/64-bit CPU IP, 2014–2015.
Figure 4‑2. Unit market share for GPU IP, 2014–2015.
Figure 4‑3. CPU-IP shipments by application category, 2015.
Figure 4‑4. GPU-IP shipments by application category, 2015.
Figure 4‑5. Mobile-device forecast, 2013–2019.
Figure 4‑6. Embedded-device and flash-memory forecast, 2013–2019.
Figure 4‑7. Consumer-electronics forecast, 2013–2019.
Figure 4‑8. Enterprise-device forecast, 2013–2019.
Figure 4‑9. CPU-IP forecast by application category, 2013–2019.
Figure 4‑10. GPU-IP forecast by application category, 2013–2019.
Figure 5‑1. Relative area and performance of ARM Cortex-A CPUs.
Figure 5‑2. Block diagram of ARM Big.Little system architecture.
Figure 5‑3. Block diagram of ARM Cortex-A7 CPU.
Figure 5‑4. Block diagram of ARM Cortex-A57 CPU.
Figure 5‑5. Block diagram of ARM Cortex-A72 CPU.
Figure 5‑6. Pipeline diagram of ARM Cortex-A53 CPU.
Figure 5‑7. Pipeline diagram of ARM Cortex-A35 CPU.
Figure 5‑8. Block diagram of ARM Cortex-R7 CPU.
Figure 5‑9. Block diagram of ARM Mali-T760 GPU.
Figure 6‑1. Andes N8 CPU in an electronic-label controller.
Figure 7‑1. Block diagram of the Xtensa microarchitecture.
Figure 8‑1. History of the MIPS ISA.
Figure 8‑2. Imagination Series6 and Series7 GPUs.
Figure 8‑3. Block diagram of MIPS P5150.
Figure 8‑4. Block diagram of MIPS P6600.
Figure 8‑5. Block diagram of MIPS I6400.
Figure 8‑6. Block diagram of Imagination Series7 GT7600 GPU.
Figure 9‑1. Block diagram of Synopsys ARC HS38 CPU with extensions.
Figure 10‑1. Block diagram of Vivante GC7000 architecture.
Figure 11‑1. Block diagram of Adapteva Epiphany CPU.
Figure 11‑2. Soft Machines roadmap.
Figure 12‑1. NetSpeed SoC design automation.
Figure 12‑2. SonicsStudio user interface.
Table 2‑1. Standard screen sizes.
Table 2‑2. Cellular technologies and data rates.
Table 4‑1. Unit market share for 32/64-bit CPU IP, 2014–2015.
Table 4‑2. Unit market share for 32/64-bit GPU IP, 2014–2015.
Table 5‑1. Key parameters for ARM 32-Bit Cortex-A cores.
Table 5‑2. Key parameters for ARM 64-Bit Cortex-A cores.
Table 5‑3. Key parameters for ARM Cortex-R and Cortex-M cores.
Table 5‑4. Key parameters for selected Mali area-optimized GPUs.
Table 5‑5. Key parameters for selected ARM performance-optimized GPUs.
Table 6‑1. Key parameters for Andes CPU cores.
Table 7‑1. Key parameters for Tensilica reference-template CPUs.
Table 8‑1. Key parameters for Imagination MIPS Warrior CPU cores.
Table 8‑2. Key parameters for Imagination Series6 graphics processors.
Table 8‑3. Key parameters for Imagination Series7 graphics processors.
Table 9‑1. Key parameters for Synopsys ARC cores.
Table 10‑1. Key parameters for Vivante GC7000 graphics processors.
Table 10‑2. Key parameters for Vivante GC7000 Lite graphics processors.
Table 11‑1. Key parameters for Adapteva Epiphany cores.
Table 11‑2. Key parameters for Beyond CPU cores.
Table 11‑3. Key parameters for Cobham Gaisler Leon3 and Leon4.
Table 11‑4. Key parameters for first-generation Cortus CPU cores.
Table 11‑5. Key parameters for Cortus APS23 and APS25.
Table 12‑1. Key parameters for ARM CCI and NIC licensable interconnects.
Table 12‑2. Key parameters for ARM CCN licensable interconnects.
Table 13-1. Comparison of low-end embedded CPU cores.
Table 13‑2. Comparison of midrange embedded CPU cores.
Table 13‑3. Comparison of high-end embedded CPU cores.
Table 13‑4. Comparison of low-end CPU cores.
Table 13‑5. Comparison of high-performance CPU cores.
Table 13‑6. Comparison of GPU cores for wearables.
Table 13‑7. Comparison of low-cost GPU cores.
Table 13‑8. Comparison of midrange GPU cores.
Table 13‑9. Comparison of high-end GPU cores.

Events

Linley Processor Conference 2017
Covers processors and IP cores used in embedded, communications, automotive, IoT, and server designs.
October 4 - 5, 2017
Hyatt Regency, Santa Clara, CA
Register Now!
More Events »

Newsletter

Linley Newsletter
Analysis of new developments in microprocessors and other semiconductor products
Subscribe to our Newsletter »