White Papers

We periodically publish white papers providing our analysis and insight on a particular processor or technology.

The following white papers are currently available:

Multi-Gigabit Ethernet Controllers for Enterprise Networks and Gaming Systems

This paper describes the markets and applications for Ethernet speeds beyond 1Gbps in client systems. It discusses NBase-T technology, which forms the basis for the 2.5GBase-T and 5GBase- T standards under 802.3bz. It then describes client implementations, including Aquantia’s new AQtion controller chip. (Note: This paper is sponsored by Aquantia, but all opinions and analysis are those of the author.) 

Easing Heterogeneous Cache Coherent SoC Design using Arteris' Ncore Interconnect IP

Heterogeneous processing has become a hallmark of mobile SoCs, but designing cache coherency across these diverse processing elements can be difficult. Standard on-chip interfaces and network-on-a-chip (NoC) technology are the first step, giving architects IP to efficiently connect compute processing elements as different as CPUs, GPUs, and DSPs. Hardware IP to enable coherent communication between different types of compute engines is the next step. This white paper describes how Arteris’ Ncore IP can help architects design processors fully supporting coherency between heterogeneous elements. The Linley Group prepared this paper, which Arteris sponsored, but the opinions and analysis are those of the author.

X-Gene 3 Challenges Xeon E5

AppliedMicro’s new X‑Gene 3 processor design combines 32 ARMv8-compatible CPU cores to deliver an estimated 550 SPECint_rate, competitive with the performance of today’s fastest Xeon E5 processors. With eight DDR4 memory channels, X‑Gene 3 even outclasses Xeon E5 in memory bandwidth, making it well suited to memory-intensive applications. AppliedMicro expects to sample the new design in 2H16, leading to production shipments in 2H17, about the same schedule as for Intel’s Skylake server products.

Beyond the Data Center: How Network-Function Virtualization Enables New Customer-Premise Services

This paper describes how network-function virtualization (NFV) and software-defined networking (SDN) will help network operators profit from greater flexibility and the faster rollout of new revenue-generating services. Important building blocks in this transformation are embedded processors optimized for networking and communications. NXP’s QorIQ processors are well positioned to meet the requirements of virtualized network services. The Linley Group prepared this paper, which NXP sponsored, but the opinions and analysis are those of the author.

Low-Power Design Using NoC Technology

Network-on-a-chip (NoC) technology is not just for high-performance SoC designs. The size and power of the NoC can scale down to accommodate even very small and low-power processors. Furthermore, the NoC helps automate the chip's power management. The NoC can also simplify designing a single die that produces multiple end products. This white paper describes how a NoC can achieve these advantages, using TI's CC26xx microcontroller as a case study. The Linley Group prepared this paper, which Arteris sponsored, but the opinions and analysis are those of the author.

Carrier Aggregation Turbocharges Mobile Apps

This white paper describes the benefits that carrier aggregation will provide for operators and users of LTE-Advanced wireless networks. Carrier aggregation enables downlink and uplink in multiple frequency bands to increase connection speed and network capacity over single-carrier LTE systems. These improvements enable higher performance in mobile devices, but require SoC designs that take full advantage of the faster data rates. Users will benefit from new and enhanced applications that exploit the capabilities that carrier aggregation will provide. The Linley Group prepared this paper, which Qualcomm sponsored, but the opinions and analysis are those of the author.

Automating Front-End SoC Design With NetSpeed's On-Chip Network IP

This white paper describes NetSpeed's NocStudio design tool and the Orion and Gemini licensable network-on-chip (NoC) products. Orion is a configurable on-chip interconnect fabric, and Gemini adds cache coherence for processor cores, acceleration engines, and other components. NocStudio is a pre-RTL design tool that enables architects to customize these NoCs and compare alternative topologies before committing the design to a C-level simulation or RTL. NocStudio is also capable of automatically generating a network topology that connects all the IP blocks in a preliminary layout that optimizes the design for performance, power efficiency, die area, low latency, and deterministic quality of service (QoS).

Achieving Energy Efficiency with EFM32 Gecko Microcontrollers

This paper describes Silicon Lab's EFM 32 Gecko Microcontroller family. This large product portfolio of 32-bit MCUs includes more than 240 devices based on the ARM Cortex-M0+, Cortex-M3, and Cortex-M4 processor cores. Despite this variety, all EFM32 MCUs are software compatible with each other, and EFM32 chips with the same package configuration are pin compatible. They also have many common peripherals and other features.

ARC HS38: Single- and Multicore CPUs for High-Speed Linux Processing on an Embedded Budget

Designers of performance-intensive, embedded SoCs running Linux or other virtual-memory operating systems must address increasing performance requirements with power budgets that are often constant or shrinking. Available processors that offer the needed performance often draw too much power, while processors that fit within the power budget lack the necessary performance. The DesignWare® ARC® HS38 multicore processor is designed specifically for embedded Linux applications and enables chip designers to create single-, dual- or quad-core configurations with an MMU and fast L2 cache. Read this white paper to learn about the ARC HS processor architecture features and new features in the ARC HS38 processor.

Always Listening, Always On: Advances in Sensory Processing

Smartphones use sensors and voice input to become aware of their surroundings and to interact more naturally with their users. Smartphone makers continue to develop more advanced capabilities, adding new types of sensors and more sophisticated voice functions. If implemented improperly, these changes can greatly reduce battery life. This paper explores the latest advances in sensory processing and how new semiconductor products can implement these features using minimal power.

Xilinx SDNet: A New Way to Specify Network Hardware

This paper examines Xilinx's SDNet specification environment and its role, both in defining elements in Software-Defined Networks, and in implementing reconfigurable network elements in both control and data plane.

Qualcomm Pushes Mobile to UltraHD

Qualcomm's new Snapdragon 805 processor redefines the mobile experience to focus on video and imaging capabilities. It is the first mobile processor with end-to-end 4K support, enabling users to capture, decode, and display video in UltraHD resolution. When paired with Qualcomm's next-generation Gobi 9x35 LTE Advanced modem chip, the platform offers the fastest cellular downloads as well. This white paper describes the momentum behind 4K video and explains how the Snapdragon 805 platform offers the best support for this emerging standard.

Analyzing The Power of Mobile SoCs: Pitfalls and Best Practices

Power is a critical part of the user experience, but assessing the power of a mobile SoC is challenging. We recommend measuring power for the entire chipset rather than the SoC alone, as this method captures system-level optimizations that the vendor has made. A full assessment of the chipset's power characteristics requires testing across a variety of use cases. A chipset that excels in one area may fare poorly in others, depending on the design choices the chip vendor has made. Many use cases measure power for a fixed task, but some cases require measuring both power and performance for a fair comparison.

Synopsys ARC HS Processors: High-Speed Licensable CPU Cores for Embedded Applications

This white paper describes the Synopsys DesignWare® ARC® HS (High Speed) processor family. ARC HS34 and HS36 are the first members of the company's newest family of licensable CPU cores for embedded applications that need 32-bit RISC performance in a small silicon footprint with minimal power consumption. The Linley Group prepared this report after evaluating ARC HS performance data and technical features. This paper is sponsored by Synopsys, but the opinions and analysis are those of the authors.

A New Era of Network Processing

This paper examines traditional network-processor (NPU) architectures, technology trends driving new requirements, limitations of NPUs and CPUs, and new architectures that overcome these challenges.

Vectoring and Bonding Renews DSL

DSL data rates have failed to keep up with those of cable and fiber networks. The maximum throughput in DSL connections is limited by the crosstalk between adjacent wire pairs bundled together in a cable or binder. Vectored-DSL technology mitigates and even eliminates crosstalk to delivers a big boost and allows Telcos to provide bandwidth similar to that offered by cable operators. Vectoring enables the VDSL2 downstream data rate to reach around 150Mbps. Using two-pair bonding, Telcos can further increase the data rate to 200Mbps or greater.

Synopsys DesignWare ARC EM Family: Efficient CPU Cores for Embedded Applications

This paper describes Synopsys’s DesignWare® ARC™ EM Processor Family, the company’s newest licensable CPU cores for embedded applications that benefit from 32-bit RISC performance with a tiny silicon footprint and minimal power consumption. According to vendor testing with EEMBC, SPEC, and other benchmarks, the newest ARC EM CPUs have excellent code density while delivering high performance using less power in a small silicon-area footprint. The Linley Group prepared this report after evaluating performance data and technical features for the recently upgraded EM4 and EM6 CPU cores. This paper is sponsored by Synopsys, but all opinions and analysis are those of the author.

AppliedMicro’s X-Gene: Minimizing Power in Data-Center Servers

In cloud data centers, power-hungry server processors drive up operating costs both directly and indirectly. As these data centers grow, cloud server providers are seeking to reduce costs by using lower-power processors. ARM technology is one approach that can provide significant power savings. AppliedMicro is developing an ARM-compatible 64-bit server processor called X-Gene that will deliver a leap forward in power efficiency.

The Precision32 Family of Mixed-Signal MCUs

This paper describes Silicon Labs’ new Precision32™ microcontrollers, the company’s first 32-bit
MCUs. In addition to the ARM-compatible CPU, the chips integrate USB and a set of analog
components along with the usual flash memory, SRAM, timers, and serial interfaces. This paper
is sponsored by Silicon Labs, but all opinions and analysis are those of the author.

QLogic's 3GCNA: SAN Leadership Meets LAN Convergence

This white paper examines QLogic's third-generation converged network adapter (CNA) technology, which combines elements from the company's Fibre Channel HBA, iSCSI HBA, and intelligent NIC product lines. This paper is sponsored by QLogic, but all opinions and analysis are those of The Linley Group.

Suite B: Classified Network Security Goes Commercial

This white paper examines the need for Suite B security, the underlying technology, chip-level requirements, and real-world implementations. This paper is sponsored by Exar, but all opinions and analysis are those of The Linley Group.

Marvell Processor Development

This paper describes the lengthy effort behind Marvell's launch of their Sheeva processor line. We examine these new processors and their applicability to communications, printers, storage, consumer, and mobile applications, and provide a peek at some next-generation CPUs. This paper is sponsored by Marvell, but all opinions and analysis are those of The Linley Group.

Single-Chip Control/Data-Plane Processors

This paper examines the trend toward combining control-plane and data-plane processing on a single chip. It discusses the technologies driving this trend, the common features of these chips, their advantages and disadvantages, and how they are being deployed today and into the future.


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