Linley Spring Processor Conference 2019

Held April 10 - 11, 2019
Proceedings available

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Agenda for Day One: April 10, 2019
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9:00am-10:00amKeynote

Keynote: A Deep Dive Into Deep Learning
Linley Gwennap, Principal Analyst, The Linley Group

Deep learning, often called AI, has become an important workload for nearly every processor and end application, including data centers, automobile safety systems, smartphones, and even microcontroller-based consumer devices. This presentation will touch on the latest trends in deep-learning accelerators, such as sparse compute, spiking neural networks, and in-memory (analog) compute. It will also discuss how these accelerators are used across a range of end applications.

There will be Q&A and a panel discussion featuring above speakers.

10:00am-10:20amBREAK – Sponsored by Arm
10:20am-12:00pmSession 1: CPU Cores

RISC-V continues to energize the CPU-core market with a new open-source ISA that has been adopted by multiple suppliers. Arm remains the leading supplier of CPU cores for client devices and microcontrollers, but it is moving into less familiar territory with its newest products. This session, moderated by The Linley Group principal analyst Linley Gwennap, highlights these two trends and contrasts the capabilities of these CPU vendors.

A New RISC-V Core IP for Low Power Yet High Performance
Frankwell Lin, President, Andes Technology

Andes offers a broad family of RISC-V core IP from entry-level to high-end embedded. This presentation will discuss a new RISC-V core, the D25F, that offers low power yet high performance. It is the first RISC-V CPU to implement the draft SIMD P-Extensions. The presentation will also provide technical and PPA information on two other recently released cores: the N22, a two-stage-pipeline entry-level RISC-V core that delivers 3.93 Coremark/MHz, and the AX25MP/A25MP for higher-performance RISC-V multicore designs.

Extending and Optimizing 64-bit RISC-V Processors
Yunsup Lee, CTO, SiFive

Modern compute workloads are evolving; they must scale performance on demand and often have real-time, deterministic requirements. Intelligence is moving from the enterprise core to the edge and requires a diverse combination of compute, storage, and acceleration in embedded form factors. This presentation will highlight recent advancements around extending and optimizing SiFive's 64-bit RISC-V processors to enable heterogeneous compute and efficiency by providing a scalable portfolio of CPU IP that can be customized according to the application requirements.

Arm Neoverse N1 Platform: Accelerating the Transformation From Cloud to Edge 
Brian Jeff, Senior Director of Product Management, Arm

As we move towards a world of 1 trillion connected devices, Internet infrastructure will be transformed from cloud to edge. Seeking to reduce operating costs, cloud data centers are redesigning hardware around alternative architectures with more heterogeneity. The Arm Neoverse N1 platform enables design flexibility in the cloud, with the power efficiency to scale all the way to edge deployments. This presentation will provide a deep dive of the platform including workload performance and platform-specific design optimizations for target applications.

There will be Q&A and a panel discussion featuring above speakers.

12:00pm-1:15pmLUNCH – Sponsored by Intel
1:15pm-2:45pmSession 2: IoT Security

The Internet of Things has a dark side: it potentially opens billions of networked devices to malicious intruders. Recent breaches have shown that strong security can't be an afterthought; hardware and software engineers must bake it into their designs from the start of a project. This session, moderated by The Linley Group senior analyst Tom R. Halfhill, will discuss technologies and industry initiatives that resist attacks from multiple vectors.

Accelerating the Path to a Safe and Secure SoC
Rich Collins, Product Manager for ARC Processors, Synopsys

As more SoC designs are deployed in safety-critical applications, functional safety becomes an important consideration in system architecture. Security is also critical for connected cars and must be considered in safety applications. This presentation will outline the key requirements for ISO 26262 as they relate to processor IP and demonstrate how a safety-management architecture for SoC safety bring-up, functional safety testing, and overall monitoring and executing safety escalations provides for deterministic safety decisions across complex SoCs.

IoT: Internet of Threats? Protect the Things!
Gijs Willemse, Vice President of Silicon IP R&D, Verimatrix

IoT devices present a juicy target for misuse. Rarely is the end goal to attack the device itself. Attackers can steal resources or information in the cloud. Or they can attack the IoT 'consumer' to access private information or hijack other devices. This presentation will explain how resource-constrained IoT devices can defend themselves against Internet-scalable attacks and how Inside Secure's Root-of-Trust engine and Secure Communication Silicon IPs can ease and bolster the implementation of these defenses.

Building Trust Across IoT at Scale
Suresh Marisetty, Principal Security Solutions Architect, Arm

The IoT comprises many diverse devices, such as surveillance cameras, smart meters, and asset trackers. No single security model can address the different threat scenarios that affect these various devices. This presentation will discuss the importance of a root of trust and introduce Arm's approach to quantifying security with different levels of testing and robustness. This approach brings consistency for silicon vendors and helps device manufacturers and software vendors to leverage and benefit from the security capabilities of these devices.

There will be Q&A and a panel discussion featuring above speakers.

2:45pm-3:05pmBREAK – Sponsored by Arm
3:05pm-4:45pmSession 3: AI at the Edge

Neural networks are a critical component of most deep-learning systems and are used for tasks ranging from natural language processing to object recognition. Whereas data centers handles most network training, inference is moving out of data centers and into edge devices, reducing latency and eliminating the requirement for cloud services. Edge systems incorporating AI include automobiles, security cameras, IoT devices, and smartphones. This session, led by The Linley Group principal analyst Bob Wheeler, will examine challenges in edge-AI as well as the IP cores available to accelerate deep learning.

AI in the Era of Connectivity
Steven Woo, Fellow and Distinguished Inventor, Rambus

In our increasingly connected world, the needs of data centers, edge computing, and mobile devices continue to evolve, as does the role of artificial intelligence in each of these locations. But critical challenges remain for enabling higher-performance, more power-efficient, and secure infrastructures supporting AI, all of which offer opportunity for the semiconductor industry. This presentation will discuss some of these challenges, as well as industry directions and potential solutions to support the continued growth of AI in the market.

A High-Throughput Low Cost Low Power Edge Inference Co-Processor
Cheng Wang, Sr. VP, Software, Architecture, Engineering, Flex Logix

NMAX is a scalable, modular high-throughput inference architecture optimized for edge applications that need to process in low batch sizes (1, 2, 4) at low cost and low power. After introducing this architecture at the 2018 Fall Processor Conference, we will disclose in this presentation the InferX X1, an edge inference coprocessor based on NMAX and optimized to run large models or large images with high throughput at low cost and low power.

Adapting the Wave Dataflow Architecture to a Licensable AI IP Product
Chris Nicol, SVP and CTO, Wave Computing

In the IP market, technologies must be flexible for integration into system-on-chip (SoC) designs; process-portable to meet the requirements of other SoC platforms; and flexible enough to address a wide range of use cases and applications. Wave's unique dataflow processing architecture provides a scalable solution for emerging AI-inference use cases in edge applications. This presentation will discuss the design and implementation trade-offs to adapt the dataflow processing architecture to deliver a synthesizable and configurable technology for integration into SoC designs.

There will be Q&A and a panel discussion featuring above speakers.

4:45pm-6:15pmReception and Exhibits – Sponsored by Intel

 

Platinum Sponsor

Gold Sponsor

Micron

Andes Technologies

Media Sponsor