Machine learning (ML) at the edge must deliver cloud-like performance within stringent power envelopes. When operating autonomous automobiles, drones, surveillance cameras, and robots, a typical CPU can't meet the ML performance requirements for many new systems, thus requiring an ML accelerator. This presentation will illustrate how the industry's first green machine-learning SoC (MLSoC) provides custom ML acceleration that delivers more than 30x improvement in frames per second per watt (FPS/W) over alternatives.

Peak FLOPs and observed FLOPS have little correlation in vector architectures. Peak FLOPs are meaningless when the architecture is stalled on memory. The key to "achieving supercomputer performance", as Dongarra has called it, is to combine a vector unit with "real" vector registers and an intelligent restructuring compiler to focus computations into the processor. This presentation will discuss SiFive's RISC-V Vector extension and the technical tradeoffs among the three components, illustrating the resulting advantages with specific benchmark performance.

eFPGA technology offers functionality similar to leading FPGA chips and is proven from 7nm to 180nm. But eFPGA designs can be iterated in less than a year, and architectures can evolve rapidly. Unlike standard FPGAs that have a bit of everything, eFPGA can focus on the acceleration functions that matter for a given application. This presentation will describe how architectures are innovating to accelerate workloads like floating-point signal processing and AI inference in both INT8 and BF16 formats.

Smartphones, digital assistants, cars, and other embedded systems are using machine learning for audio and speech applications. Typically, neural-network models are hand coded to fit within the memory and power constraints of the system. The latest capabilities of TensorFlow can provide an end-to-end framework enabling users to train and efficiently deploy their models. This presentation will walk through the details of building a keyword-detection model and deploying it on a HiFi DSP using the TensorFlow tool chain.

Contextual awareness is enabling enriched user experience in applications such as robotics, wearables, and conversational assistants. It involves processing of multiple sensors such as cameras, radars, microphones, and motion sensors, and includes various computer vision, voice processing, and neural network workloads. This presentation will introduce a new scalable vector DSP architecture for contextual awareness processing, providing floating-point arithmetic, optimized linear-algebra operations, and an enhanced pipeline for higher quality and power efficiency.

A transformation is occurring in high-end embedded applications as Internet infrastructure spreads from the cloud to the edge. Performance requirements are increasing, but designers must account for power and area limits. These changes are driving greater use of configurable multicore solutions and specialized hardware accelerators. This presentation will introduce a new multiprocessor cluster architecture that is highly scalable, enabling it to achieve very high performance for storage, automotive, networking and other high-end embedded applications.