Linley Fall Processor Conference 2021

Coming October 20-21, 2021
Hyatt Regency Hotel, Santa Clara, CA

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Agenda for Day One: Wednesday October 20, 2021
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9:00am-9:50amKeynote:

Keynote: AI Moves From the Cloud to the Edge
Linley Gwennap, Principal Analyst, The Linley Group

For chip vendors, AI has evolved from a product to a feature, with AI acceleration appearing in server processors, PC processors, FPGAs, and vast array of edge devices. In the data center, new chips focus on improving performance per watt. Architecture innovation is particularly rampant at the edge, where power limitations are stringent and software stacks are smaller. Edge chips target a range of applications from battery-powered sensors to powerful camera-based systems. This presentation will describe the latest architecture trends for AI accelerators of all types.

There will be a Q&A following this presentation.

9:50am-10:10amBreak - Sponsored by Flex Logix
  Track A Track B
10:10am-11:45amSession 1: Applying Programmable Logic to AI Inference

As AI workloads evolve, deep-learning accelerators may fail to deliver adequate performance for new neural-network models. Adding AI to existing edge designs may require unique or proprietary processing or I/O. This session, moderated by The Linley Group principal analyst Bob Wheeler, examines how programmable logic can address these challenges in AI inference.

A Flexible Yet Powerful Approach to Evolving Edge AI Workloads
Cheng Wang, Sr. VP, Software Architecture Engineering, Flex Logix

This presentation will explore how machine learning models continue to evolve with new structures and approaches such as transformers offering better accuracy, higher throughput and lower training requirements.  Flex Logix' InferX technology offers a unique dynamically reconfigurable hardware approach to AI inference acceleration that is well suited to expressing new model types.

Optimized ML Solution with Lattice FPGA
Sreepada. V. Hegade, Sr. Manager – ML Software and Solution, Lattice Semiconductor

Machine learning has successfully penetrated many domains, each with unique requirements. The evolution of Convolution Neural Networks (CNN) has contributed significantly to bringing intelligence to the edge. The inference of neural networks with resource constrained devices comes with its own challenges in meeting performance, accuracy, power, and cost. Lattice sensAI enables application developers to create well-balanced solutions. This presentation will discuss how FPGAs allow for quick adoption of emerging neural network topologies and how CertusPro-NX enables developers to meet their objectives.

How to Overcome the Pain Points of AI/ML Hardware
Kent Orthner, Vice President, Architecture, Achronix

AI/ML hardware faces three common pain points: memory bandwidth, computational throughput and on-chip data movement. In this presentation, we reveal key capabilities of the Achronix Speedster7t FPGA family that offers a 2D NoC, GDDR6 and machine learning processors (MLPs) to alleviate these pain points. Offering a balance of speed, power and cost, FPGAs and eFPGA IP are ideal platforms for AI/ML inferencing solutions that provide the flexibility of a GPU while performing at speeds similar to an ASIC.

There will be Q&A and a panel discussion featuring above speakers.

Session 2: SoC Design

Silicon designers are often tasked with the impossible, delivering high-performance and healthy silicon in compressed design cycles. This session, moderated by The Linley Group senior analyst Aakash Jani, discusses IP and clock architectures that help boost performance and reduce design times across various segments. Additionally, we will see how telemetry and AI provide insight before and after silicon deployment to lift silicon yield and post-packaging longevity.

Monitoring Electronics’ Performance in Production and In-Field Through Chip Telemetry
Alex Burlak, VP Test & Analytics, proteanTecs

In order to scale the robustness, cost and performance of advanced electronics, intelligence must be designed in, to provide manufacturers and service providers continuous visibility. This presentation will discuss a new approach to performance monitoring of mission-critical systems, from design and production, to the field. AI-driven analytics, based on in-chip Universal Chip Telemetry (UCT), provide deep data throughout the SoC’s lifecycle, allowing for performance optimization and predictive reliability monitoring at every stage.

60% of SoCs Lose 30-50% Performance Due to Clock Networks
Mo Faisal, President and CEO, Movellus

Believe it or not, clock distribution networks are incredibly inefficient. Learn three simple questions you can ask to reveal these inefficiencies. Hint: It's not an engineering issue; it's an architecture and IP issue. Architecture innovation has happened in Processing Elements, data delivery (NOCs), and memory, but clocks are still buffers and wires. Find out how adding intelligence and architectural innovation to the clock distribution network can eliminate power supply droop (workload), reduce PVT/OCV effects (throughput/power), and reduce/eliminate current noise (power).

224Gbps Data Rates, The Next Big Step
Clint Walker, VP of Marketing, Alphawave IP

To keep up with the connectivity bandwidths required by networking, data-center and 5G markets, electrical signaling is moving from 56Gbps to 112Gbps, and is on a path to the next speed of 224Gbps. Recent DSP innovations are enabling 224Gbps transceivers with more than 40dB of insertion loss. This talk will present Alphawave’s roadmap for very high speed SerDes and share insights into its 224Gbps SerDes technology.

This session will include Q&A after each presentation.

11:45am-1:15pmLUNCH - Sponsored by Intel
1:15pm-2:50pmSession 3: Edge-AI Software

In edge applications, customers need to carefully balance the accuracy, performance, and power dissipation of their AI implementations. Software tools are critical to enabling these tradeoffs while taking full advantage of hardware optimizations. This session, led by The Linley Group senior analyst Mike Demler, will discuss how vendors are addressing these software challenges to advance AI at the edge.

Real-time Embedded Vision Solutions with the InferX SDK
Jeremy Roberson, Technical Director and AI Inference Software Architect, Flex Logix

Embedded vision applications are proliferating across multiple industries.  Key metrics include high accuracy with low latency in batch-size = 1 environments. This presentation will cover the InferX Edge Inference SDK, which is responsible for compiling the model and enabling inference on the X1 Inference Accelerator while preserving the model's accuracy.

Software’s Lead Role in Productizing High-Performance Edge AI Products
Daniel Chibotero, Chief Architect, Hailo Technologies

In this presentation we will discuss the importance of a robust software toolchain in optimizing the performance of AI acceleration at the edge, and the role software plays in edge AI innovation and adoption. We will discuss flexibility, versatility and upgradability aspects and their impact, as well as software developer tools which play a key role in facilitating state-of-the-art AI applications in edge products. Lastly, we will look at product implementation examples which illustrate the topics discussed throughout the presentation.

Achieving Real-Time High-Resolution Video Inference at Ultra-Low Power
Ravi Setty, SVP Engineering , Cofounder, Roviero

AI implementation in edge devices is still very limited due to the power consumed by the compute and associated memory. Models with good accuracy are still large in size and contribute to high memory and power consumption. Roviero’s CortiOne offers a full stack solution with its CortiSoft fully automated compiler tool chain along with associated compute IP as the solution. The CortiSoft compiler optimizes memory accesses such that the model memory is in a sleep state 99% of the time, thereby dramatically reducing power consumption while maintaining full accuracy.

There will be Q&A and a panel discussion featuring above speakers.

Session 4: High-Performance Processors

Data centers and network infrastructure demand the highest-performance processors. In response, vendors are pushing the limits of core counts, cache size, I/O bandwidth, IC process, packaging, and software. This session, led by The Linley Group principal analyst Linley Gwennap, will discuss how companies are using these technologies to deliver leading-edge processors.

Next-Gen Intel Xeon Scalable CPU - Sapphire Rapids
Arijit Biswas, Senior Principal Engineer, Intel

Combining Intel’s Performance-cores with new accelerator engines while delivering new memory and IO technologies, Sapphire Rapids sets the standard for next-generation data center processors. At the heart of Sapphire Rapids is a tiled, modular SoC architecture that delivers significant scalability while still maintaining the benefits of a monolithic CPU interface thanks to Intel’s EMIB packaging technology. Sapphire Rapids delivers substantial compute performance across traditional datacenter usages with unique purpose-built optimizations for performance on elastic compute models like cloud microservices and AI.

The SystemReady Standards Program: Enabling Systems Where Software ‘Just Works’
Dong Wei, Lead Standards Architect and Fellow, Arm

Systems designed to ‘just work’ for the end user, able to install and run generic operating systems out of the box, must follow a set of minimum processor and system architecture requirements and firmware recipes. We present a comprehensive standards-based approach, Arm System Ready, which provides requirements, defined with the Arm ecosystem, that can be applied to a broad range of devices from cloud datacenters to edge and IoT. It reduces or eliminates the cost of customization for the system firmware and kernel build. 

CPU Embedded SRAM Trends and 3D-Cache Analysis
Yuzo Fukuzaki, Senior Technology Fellow, TechInsights

The growing performance gap between the CPU and main memory is a well known issue in processor chips. The primary solution is embedded multilevel cache memories. Designers must balance functional demands to fill the performance gap with increasing die area and cost. In this presentation, we discuss embedded memory trends in multiple chip types and future memory integration items such as 3D cache including analysis of an early design.

This session will include Q&A after each presentation.

2:50pm-3:10pmBREAK - Sponsored by Flex Logix
3:10pm-4:45pmSession 5: Low-Power Sensing & AI

The real world is analog, teeming with natural and man-made waveforms that span from subsonic to millimeter-wave frequencies. Sensing, receiving and transmitting such signals typically requires specialized process technologies, whereas analyzing them demands efficient AI processing. This session, moderated by The Linley Group senior analyst Mike Demler, examines technologies that enable next-generation AI-enabled IoT devices.

Intelligent Edge AI: The Future is Now
Anil Mankar, Cofounder, Chief Development Officer, BrainChip

BrainChip’s Akida NPU addresses the demand for ultra-low power and incremental learning, inspired by the biology of human brain processing. This technology is key to the future of Intelligent AI at the Edge. Advanced neuromorphic computing delivers a pathway to new technologies driving the ecosystem, and solves problems in machine learning such as privacy, latency and reliance on the cloud. In this session, BrainChip will demonstrate real-time use cases and share recent developments of its Akida event domain neural processor.

Core Edge AI Processors: From In-Memory to At-Memory
Stephen Bailey, CTO, Syntiant

Syntiant was founded to deliver edge AI solutions with chips based on in-memory, analog deep-learning processing technology.  We discovered early in our journey that demand for these solutions was more immediate and diverse than anticipated, and that a custom at-memory, digital deep-learning processor architecture would provide the required cost, performance and efficiency while providing chip-process portability.  In this talk, we will briefly describe this journey and share architectural insights and performance comparisons of the Syntiant Core 2 processor found in our Neural Decision Processor (NDP) chips.

Low-Power Semiconductor Design Innovations for IoT Applications
Pirooz Parvarandeh, CTO, GlobalFoundries

As AI moves ever closer to the edge, the focus on controlling and reducing power consumption is even more intense as the number of edge devices and the amount of data soars. This presentation examines design considerations for state-of-the-art low power IoT/edge devices from system architecture to process technology, with implementation details for precision analog, wireless, computing and memory.

This session will include Q&A after each presentation.

Session 6: Server Acceleration

As the industry embraces heterogeneous computing, vendors are delivering a new generation of application-optimized accelerators. These new chips drive both throughput and efficiency, separating them from CPUs and GPUs. Led by The Linley Group principal analyst Bob Wheeler, this session examines solutions ranging from IP to chips and supporting software that exemplify this trend.

Datacenter Accelerators Using RISC-V
John Min, Director of NA Field Application Engineering, Andes Technology

Datacenter accelerators for demanding compute tasks such as AI and analytics are projected to grow rapidly through 2030 and to generate more revenue than datacenter CPUs at that time. In this talk, we will show how Andes RISC-V processor IP NX27V leverages RISC-V’s strength to offer two of the most important features sought by accelerator SoC designers: powerful vector processing and efficient integration with hardware engines. We will also discuss the related system architecture and programming support.

Accelerating ML Workloads with Energy-Efficient High-Performance RISC-V Processors
Darren Jones, Vice President of VLSI Engineering, Esperanto Technologies

Esperanto Technologies has developed the first of a family of accelerator chips for large scale machine learning inference applications. Esperanto’s approach uses over 1,000 general-purpose RISC-V cores, each equipped with a vector/tensor unit optimized for common machine learning algorithms and data types. Esperanto’s chip is highly energy-efficient, fully programmable, and adaptable as algorithms change. By leveraging the simplicity of the RISC-V instruction set and carefully designing with low-power techniques, Esperanto’s chip preserves many benefits of general-purpose programming while simultaneously delivering excellent performance and energy efficiency.

Success Metrics and Challenges for Deploying AI Inference
Robert Beachler, VP of Product, Untether AI

Hardware is necessary but insufficient to deploy high-throughput, low-latency AI inference. The software development kit (SDK) is critical to transform a trained neural network into a deployable model with the necessary performance and accuracy targets. This talk will explain the optimization steps required to deploy accurate, performant, and efficient neural networks on sequential and spatial AI acceleration architectures.
 

There will be Q&A and a panel discussion featuring above speakers.

4:45pm-6:15pmReception and Exhibits – Sponsored by Intel

 

Premier Sponsor

Platinum Sponsor

Gold Sponsor

Andes Technologies

Silver Sponsor

Industry Sponsor