Linley Spring Processor Conference 2019

April 10 - 11, 2019
Hyatt Regency, Santa Clara, CA

» Events  |  Agenda Day One  |  Agenda Day Two  |  Proceedings

The Linley Spring Processor Conference was held on April 10 - 10 at the Hyatt Regency Hotel in Santa Clara, CA. Proceedings are now available at the above link.

This two-day event is the only one of its kind focused on the processors and IP cores used in deep learning, embedded, communications, automotive, IoT, and server designs. Principal Analyst Linley Gwennap opened the conference with his keynote note: A Deep Dive Into Deep Learing.The second day started with a keynote from Red Hat, Jon Masters covering security concerns facing contemporary microarchitectures. The remainder of the program included more than 17 talks and panel discussions covering a broad range of topics, such as:

A New RISC-V Core IP for Low Power Yet High Performance
Frankwell Lin, President, Andes Technology

Extending and Optimizing 64-bit RISC-V Processors
Yunsup Lee, CTO, SiFive

Arm Neoverse N1 Platform: Accelerating the Transformation From Cloud to Edge
Brian Jeff, Senior Director of Product Management, Arm

Accelerating the Path to a Safe and Secure SoC
Rich Collins, Product Manager for ARC Processors, Synopsys

IoT: Internet of Threats? Protect the Things!
Gijs Willemse, Vice President of Silicon IP R&D, Inside Secure

Building Trust Across IoT at Scale
Suresh Marisetty, Principal Security Solutions Architect, Arm

AI in the Era of Connectivity
Steven Woo, Fellow and Distinguished Inventor, Rambus

A High-Throughput Low Cost Low Power Edge Inference Co-Processor
Cheng Wang, Sr. VP, Software, Architecture, Engineering, Flex Logix

Adapting the Wave Dataflow Architecture to a Licensable AI IP Product
Chris Nicol, SVP and CTO, Wave Computing

DL Boost: Embedded AI Acceleration in Intel Xeon Scalable CPUs
Ian Steiner, Xeon Scalable CPU Lead Architect, Intel

Intel Nervana Neural Network Processor: Redesigning AI Training Silicon
Carey Kloss, VP and GM of AI Hardware, Intel

DDR5: Mainstream Memory That Maximizes Effective Bandwidth
Brian Drake, Senior Business Development Manager, Micron

Opposites Attract: Customizing and Standardizing IP Platforms for ASIC Differentiation
Carlos Macian, Senior Director AI Strategy and Products, eSilicon

Adapting SoC Architectures for Types of Artificial-Intelligence Processing
Matthew Mangan, Applications Engineer, ArterisIP

Freedom Revolution: Customizable RISC-V AI SoC Platform
Krste Asanovic, Co-Founder & Chief Architect, SiFive

A Multipurpose Hybrid DSP and Controller Architecture for IoT and Wireless
Uri Dayan, Team Leader, Processor Architecture, CEVA

High Resolution, Low-Power, Programmable DSPs Optimized for Radar Sensors
Pierre-Xavier Thomas, Engineering Group Director, Tensilica DSP SW Group, Cadence

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Micron

Andes Technologies

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