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Cerebras Performs Extreme Training
The company hopes to meet the demands of huge neural networks by offering its new MemoryX and SwarmX systems, which aim to reduce GPT-3 training time to less than one day.
Tesla D1 Tackles AI Training
In a surprising move, Tesla has developed its own AI training accelerator. The D1 design crams 25 chips into an enormous wafer-scale package that generates an industry-leading 9 petaflop/s.
Alder Lake Extends Battery Life
Alder Lake is Intel’s first mainstream PC processor with a hybrid architecture, combining big and small cores to increase both performance and battery life.
Mount Evans Puts Intel in DPU Range
The company recently disclosed architectural details of its first data-processing unit, combining a control plane and a programmable data plane to handle Ethernet speeds up to 200Gbps.
Sapphire Rapids Spans Tiles
The next-generation Xeon processor is Intel’s biggest leap forward in years, delivering greater core counts, more per-core performance, integrated accelerators, and the latest memory and I/O interfaces.
Golden Cove Adds Matrix Units
Intel’s new flagship CPU microarchitecture delivers a big performance boost for general-purpose code while AI operations increase 8x using the new Advanced Matrix Extensions (AMX).
Gracemont Bulks Up in Performance
Intel’s family of “little” CPUs hits a bold new performance level by doubling the execution width and making other changes, offering a 20% jump in per-clock performance over its predecessor.
Intel Stacks Tiles on Ponte Vecchio
The new high-performance GPU is an engineering marvel, using Intel’s EMIB and Foveros technologies to create a heterogeneous processor combining 47 discrete die (tiles) built in five different process nodes.
AI-Camera Chips Sharpen Surveillance
Ambarella is sampling the CV5S and CV52S, which support 8K and 6K resolution, respectively. Realtek’s RT3916N handles 5 megapixels at 30fps, targeting lower-cost smart-camera systems.
ArchiTek Offers Virtual Engines
A Japanese startup has developed a configurable architecture that uses multiple fixed-function engines to increase power efficiency for a broad range of workloads in AI-based edge systems.
Telum Adds AI Accelerator to IBM Z
IBM’s new Z-series mainframe processor sets an industry record with more than 512MB of on-die memory and is the first high-end processor to ship with an integrated deep-learning accelerator (DLA).
Chipmakers Boost AI Efficiency by 5x
As wafer costs rise sharply, chip designers are working to boost area efficiency and performance. Our analysis of the newest flagship smartphone processors reveals that efficiency increased by up to 5x from generation to generation.
Marvell Adds Innovium Cloud Switches
Hot on the heels of closing its Inphi acquisition, Marvell announced an agreement to buy switch-chip startup Innovium. The deal will give it a leading position in data-center switching.
Renesas R-Car Drives Digital Cockpits
The R-Car Gen3e line offers new cost-saving configurations along with performance and functional-safety improvements for digital-instrument clusters and infotainment systems in entry-level and midrange vehicles.
Mali-G78 Catches Up to Apple GPU
Apple’s new A14 GPU is blurring the line between PC and mobile performance, but the design offers less of a performance increase than previous generations, allowing competitors to regain ground.
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