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Achronix eFPGA Serves AI Two Ways

January 15, 2019

Author: Bob Wheeler

It’s a classic chip-design conundrum. By the time you freeze your specification and then design, verify, tape out, and sample silicon, customer requirements have changed. To make matters worse, in the world of AI, neural-network models are evolving at lightning speed. If your deep-learning accelerator can’t efficiently map the newest models, someone else’s probably can. A great challenge in accelerator design is therefore to find the sweet spot between flexibility and efficiency. Presently, FPGAs occupy that middle ground between general-purpose processors and purpose-built accelerators.

To address this challenge, Achronix recently introduced the Speedcore 7t, its 7nm embedded-FPGA (eFPGA) intellectual property (IP). This fourth-generation (Gen4) architecture adds a machine-learning-processor (MLP) block to the menu from which customers configure their core. The MLP is essentially a DSP block optimized for neural-network matrix math. The Speedcore 7t arranges blocks in homogeneous columns of logic (LUT6), block RAM (BRAM), logic RAM (LRAM), and MLPs. On the basis of customer specifications, the company lays out a block with X columns of Y height.

In addition to the new MLP block, Achronix enhanced its Gen4 architecture relative to the prior-generation Speedcore it delivered in 2016. It has already released Gen4 support—excepting MLP—in its Ace design tools. Ace support for MLP blocks is due in 1Q19. All Speedcore 7t IP is available now, and Achronix plans to release a 16nm Gen4 design in mid-2019. More surprisingly, it plans to introduce 7nm Speedster FPGA chips (not just IP) in 1H19. Achronix is first to deliver eFPGA IP for 7nm technology, and customers in all segments will benefit from Gen4 enhancements.

Subscribers can view the full article in the Microprocessor Report.

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