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Ceva’s BX Hybrid Boosts DSP Engine

February 5, 2019

Author: Mike Demler

Ceva’s new BX DSP cores offer upgrades to the first-generation X-series models, which employ a hybrid architecture combining multicore scalar CPUs for control functions with a highly configurable five-way SIMD/VLIW DSP engine for signal processing. The new intellectual property (IP) core tightens security by using a TrustZone-like memory subsystem to isolate secure applications from nonsecure ones. Architectural enhancements double the fixed-point DSP performance compared with the previous generation, and floating-point DSP operations receive up to an 8x boost. The single-core BX1 targets NB-IoT basebands and sensor fusion, and the dual-core BX2 targets 5G PHY control, multi-microphone beam forming, and speech-recognition neural networks. Both models are available now to lead customers, and the company plans to release them for general licensing by the end of 1Q19.

The single-CPU BX1 and dual-CPU BX2 are similar to the previous X1 and X2, respectively, but they increase the maximum pipeline depth from 10 stages to 11. For designs manufactured in 7nm technology, Ceva expects the cores to run at up to a 2.0GHz clock frequency. CPU performance rises slightly from 4.3 CoreMarks per megahertz in the X2 to 4.5 in the BX2.

The multipurpose BX IP cores will compete against Arm’s Cortex-M4 and Cortex-M7 CPUs with DSP extensions, as well as the latest Cortex-M33. They improve on the first-generation X-series, but they’re also likely to attract Cortex-M customers that need better DSP performance.

Subscribers can view the full article in the Microprocessor Report.

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