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MIPS Openly Challenges RISC-V

April 2, 2019

Author: Linley Gwennap

In a bold move, MIPS is offering its eponymous instruction-set architecture (ISA) to developers without any license fees or royalties. The strategy, called MIPS Open, is an attempt to boost interest in and usage of the venerable architecture while balancing the company’s need to maintain a revenue stream. The MIPS Open community is now on line, and the company has formed a committee to advise on managing the ISA and developing future extensions.

More than 8.5 billion MIPS chips have shipped over three decades, showing that the ISA is production ready and built to handle a variety of applications ranging from microcontrollers and workstations to networking and automotive safety. During this time, the team has developed a broad instruction set with extensions to support this range of systems. MIPS Open comprises Release 6, the most recent version of the full ISA.

The company will also release one of its older CPU cores, microAptiv, with a similar no-fee license. This core is similar to Cortex-M4 in performance and DSP extensions, but Arm users must pay a license fee for the M4 and other recent CPUs. MIPS continues to offer other MIPS cores, including newer M-series models as well as the more powerful I- and P-series, under standard licensing terms and fees.

The open-source RISC-V architecture has built considerable momentum in the past two years, but MIPS Open boasts considerable advantages. For example, RISC-V currently provides few ISA extensions, although additional extensions are in the committee process. To avoid software fragmentation, MIPS Open offers a certification process, which RISC-V lacks. MIPS Open also includes a greater degree of patent protection. These characteristics will particularly appeal to large companies that want to avoid high ISA license fees but are uncomfortable with RISC-V.

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