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Hailo Illuminates Low-Power AI Chip

June 25, 2019

Author: Mike Demler

Hailo (pronounced “hey-lo”) is entering the highly competitive AI inference-engine market with a chip that runs the entire ResNet-50 neural network using only on-chip SRAM and just 1.7W. Running that network on 224x224 images, its Hailo-8 processor delivers 672fps, or 395fps per watt—nearly 20x the power efficiency of Nvidia’s Xavier chip. The company has yet to report any customers, but it’s offering early access to its prototype-development platform, which includes a software stack that supports the TensorFlow deep-learning framework. Hailo plans to begin volume production of the consumer-grade device in 2H19, followed by an automotive-grade version in 1H20.

Hailo-8 employs a data-flow architecture, but unlike most deep-learning accelerators (DLAs) based on that technique, it doesn’t rely on a single set of dedicated function blocks for all neural-network convolution, pooling, and activation layers. Whereas other data-flow processors only employ temporal resource allocation, Hailo-8 employs spatial allocation as well. For example, rather than handling all convolution layers on one large systolic array of multiply-accumulate (MAC) units, the chip dynamically configures a heterogeneous array of compute, control, and memory units to separately handle each neural-network layer. The company calls Hailo-8 a structure-defined data-flow architecture, since each neural-network model maps to a different resource-allocation graph.

The company positions Hailo-8 for ADAS and autonomous driving. Although Hailo-8 delivers impressive power efficiency, it’s not a complete SoC—it must connect to an automotive processor to handle other ADAS functions. Even though that requirement negates some of its advantage, Hailo-8 gives customers a low-power coprocessor to offload the CPUs in their electronic control units (ECUs).

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