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Marvell Upgrades to Octeon TX2

March 17, 2020

Author: Tom R. Halfhill

Marvell is shipping next-generation Octeon Fusion processors for 5G macrocell base stations and is sampling Octeon TX2 processors for base stations and other network infrastructure. All debut a new Arm-compatible 64-bit CPU core, 25Gbps serdes, PCI Express Gen4, and Octeon’s first L3 caches. The largest chip has 36 cores, runs at 2.4GHz, and can forward up to 220 million packets per second (Mpps). It’s the first major Octeon update since Marvell gained these product lines by acquiring Cavium in 2018.

Octeon TX2 succeeds the TX-series of high-performance networking processors that Cavium announced in 2016. The new Octeon TX2 products comprise the CN92xx-series (12–18 cores), CN96xx-series (18–24 cores), and CN98xx-series (30–36 cores). The first two series began sampling in mid-2019, and the CN98xx is scheduled to sample next quarter. We estimate CN92/96xx volume production will start in 4Q20 followed by the CN98xx in 1Q21.

The Octeon Fusion family augments the basic TX2 design with DSP cores, additional hardware accelerators, and radio interfaces to handle Layer 1 processing in macrocells. The newest is the 5G-capable CNF95xx, which upgrades Cavium’s CNF75xx from 2015. It’s the only standard baseband processor for 5G macro base stations, and it’s already shipping to Samsung. Marvell is developing a Fusion-based semicustom ASIC for Nokia.

By contrast, Octeon TX2 chips appeal to a wider market. In addition to handling Layer 2 and Layer 3 base-station processing, they target enterprise networking equipment, security appliances, and network-edge computing at the service-provider level. At the low end, they compete with some Intel, Broadcom, and NXP chips. At the high end, they compete with x86 processors that are less integrated but provide better per-core throughput and more threads.

Subscribers can view the full article in the Microprocessor Report.

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