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Certus-NX Extends Lattice Lineup

June 30, 2020

Author: Linley Gwennap

Certus-NX is the second member of Lattice’s Nexus FPGA family, bringing the benefits of 28nm FD-SOI technology to new applications. Whereas the initial CrossLink-NX design focuses on bridging image sensors, the new models target general-purpose FPGA applications by adding hard cores for Ethernet and encryption. Certus-NX also adds analog-to-digital converters (ADCs) for sensors and motor control. It carries forward the previous design’s PCIe interfaces, programmable-logic fabric, and flexible I/O. The new product is sampling to lead customers, with production slated for October.

Nexus is the industry’s first FD-SOI FPGA, and this technology offers lower power: the chips use back bias to reduce leakage current by up to 75% compared with standard CMOS. Lattice shows a similar total-power advantage for Certus-NX relative to competing FPGAs with similar gate counts. The new product comes in two models: the Certus-NX-17 has 17,000 logic cells (LUTs), and the Certus-NX-40 has 39,000. The logic fabric also includes embedded memory and 18x18-bit multipliers for DSP functions. A “large RAM” provides up to 2.5Mbits of additional storage.

A hard crypto block accelerates the elliptic-curve (ECDSA) algorithm for boot-code authentication and AES for bulk encryption; no other FPGA with fewer than 100,000 logic cells includes an ECDSA block. For Ethernet designs, the chip combines a dedicated clock-and-data-recovery (CDR) circuit with enough LUTs to implement the Ethernet protocol. In this way, it can create an SGMII connection to an external PHY chip. For higher-speed communication, the Certus-NX-40 model provides hard logic for a PCIe Gen2 controller. This interface operates a single lane at up to 5Gbps. Both models have two 12-bit ADCs, each operating at up to one million samples per second (Msps). 

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