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Xilinx Reduces Power for 5G Radios

December 8, 2020

Author: Bob Wheeler

After shipping three RFSoC generations, Xilinx will harden its digital front end (DFE) in what it calls the RFSoC DFE. Slated for 1H21 sampling, the new device will halve power dissipation relative to the prior-generation RFSoC with equivalent bandwidth. Alternatively, it will double bandwidth while reducing power by 30%. It will also extend direct-RF converters to 7.125GHz, marking the third improvement to the company’s integrated ADCs in three years. The RFSoC DFE targets 5G-infrastructure (RAN) equipment ranging from macrocell radio heads to millimeter-wave fixed-wireless access. Xilinx withheld full device details including part numbers, but it considers the new chip part of the 16nm UltraScale+ family.

For the RFSoC DFEs, Xilinx is hardening the digital-predistortion (DPD) and crest-factor-reduction (CFR) functions it previously supplied as soft intellectual property (IP). This change will reduce power for these functions by 80%. Because the hard DPD and CFR blocks are much smaller, the company doubled instantaneous bandwidth and made other performance improvements as well. Both blocks now handle 400MHz of bandwidth, enabling the use of ultrawideband GaN power amplifiers. The RFSoC DFEs also include hardened blocks for digital up- and down-conversion, channel filtering, P/Q resampling, and receive equalization. Customers can insert programmable logic between any hardened blocks in the transmit and receive chains to enhance or update the DFE.

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