Startup Esperanto Technologies has designed a chip with a thousand tiny RISC-V cores based on its ET-Minion design. Each core has a custom tensor unit that offloads the matrix multiplication common in neural-network inferencing; working together, the Minions can perform 139 trillion INT8 operations per second (TOPS) when operating at 1.0GHz. Yet the ET-SoC-1 design is estimated to consume only 20W in typical operation. This power efficiency is suited to both data-center accelerators and network-edge applications.

The chip has taken a long road to market. Esperanto completed its RTL design in September 2018 in preparation for a mid-2019 tapeout, but completing the design took far longer than expected. It expects to tape out to TSMC soon; if so, we expect samples in 2Q21 and full production in 1H22. To support this effort, the company has a total of $82 million in funding and a staff of more than 100 employees and full-time contractors.

The chip contains 34 tiles that each comprise 32 ET-Minion cores, for a total of 1,088 cores and 136MB of SRAM. The chip also features four supervisory ET-Maxion CPUs, an eight-lane PCI Gen4 interface, and four 64-bit DRAM interfaces. The company withheld the die size for the 24-billion-transistor chip, which we expect measures about 300mm². It plans to offer the chip standalone, on a PCIe card, and in the Dual M.2 form factor that Facebook favors. A Glacier Point card can hold six of these M.2 modules in a dense power-efficient design. Using this card, the Esperanto modules can achieve more than 800 TOPS with a typical power of 120W. The company plans to disclose neural-network benchmark results once it completes silicon characterization.