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Andes Scales Up Its RISC-V

February 2, 2021

Author: Bob Wheeler

Andes converged its superscalar RISC-V CPU with multicore scaling to create its most powerful cluster to date. The AX45MP targets high-performance applications across diverse markets such as AR/VR, edge AI, automotive infotainment and ADAS, video processing, networking, and storage. Andes claims multiple design wins, having released initial RTL to customers in 3Q20; it expects general availability during 1H21. In addition to the 64-bit AX45MP, the 45-series includes the 32-bit A45MP. The company’s new flagship RISC-V core competes with SiFive’s U74MC, which preceded it by about two years.

At the cluster level, the A45MP and AX45MP are similar to the scalar A25MP and AX25MP cores that Andes announced in 2019. The MP cluster combines up to four CPUs with a coherence manager and L2-cache controller, providing a 128-bit AXI-master interface to the rest of the SoC. The 45-series comprises the company’s first superscalar CPUs, and they extend the pipeline to eight stages compared with five in the 25-series. The CPUs implement dynamic branch prediction with a 256-entry branch target buffer. Andes rates the AX45 at 5.50 CoreMarks per megahertz, a 56% boost relative to the AX25. The CPU achieves a worst-case clock speed of 1.2GHz in 28nm technology and a typical 2.4GHz in 12nm technology.

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