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i.MX8ULP Uses FD-SOI to Cut Power

March 23, 2021

Author: Aakash Jani

NXP has extended its i.MX8 series to serve battery-powered devices by offering the i.MX8ULP and i.MX8ULP-CS, replacing the older i.MX7ULP. The new models upgrade to more modern CPUs including Cortex-A35 and Cortex-M33. They employ Samsung’s 28nm FD-SOI technology to minimize SRAM leakage and overall power consumption. The 8ULP is scheduled to sample in 2Q21 and reach production in 1H22; the 8ULP-CS should follow about six months later.

As with the 7ULP, customers have two CPU-configuration options for the 8ULP. The new design’s application-processor domain supports one or two Cortex-A35 cores with 32KB instruction and data caches. The 64-bit A35 replaces the 7ULP’s ancient 32-bit Cortex-A7. It delivers 40% more performance at the same power, boosting integer IPC by 6% and floating-point IPC by 36%. The A35 integrates a dedicated power-management unit, which reduces power consumption by 7% per core. NXP doubled the L2 cache size to 512KB, further decreasing power by limiting external-memory reads.

In the real-time domain, the 8ULP integrates a single Cortex-M33F with DSP extensions, upgrading the 7ULP’s Cortex-M4. The M33F brings single-precision floating-point support to the real-time domain, enabling medical and industrial applications to run on the low-power processor. For general integer code, it scores 3.86 CoreMarks per megahertz (a proxy for instructions per cycle)—13% better than the M4. The new real-time CPU features 32KB instruction and data caches, which are 4x larger than the 7ULP’s.

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