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R-Car V3U Runs Lockstep Neural Nets

March 23, 2021

Author: Mike Demler

The new Renesas R-Car V3U offers more-extensive functional-safety features and much greater performance than its predecessor, the R-Car V3H. To meet ISO 26262 requirements, most ADAS processors implement hardware redundancy only in an isolated safety island, but the V3U employs that technique in all the compute subsystems, including the deep-learning accelerators (DLAs). Although the company positions a single chip for Level 2 ADASs and dual chips for Level 3, the V3U delivers greater peak throughput—66 trillion operations per second (TOPS)—than the processors in most Level 4 autonomous vehicles (AVs) now under development.

The V3U implements redundancy in five functional domains using a technique called dual-core lockstep (DLCS). The control domain applies the most common technique: its two Cortex-R52 CPUs manage real-time ASIL D–compliant operations throughout the SoC, and they control security as well as external communications to the automotive bus. The application domain integrates eight Cortex-A76 CPUs that run as four lockstep pairs; the computer-vision (CV) domain allows two of the three DLA cores to run in lockstep, sacrificing one-third of the possible neural-network throughput. The interconnect block applies lockstep operations to I/Os, and the memory interface permits lockstep DRAM operations.

The R-Car V3U is a 230mm2 chip that TSMC manufactures in 12nm technology. Renesas is now sampling the processor, but because of long automotive-design cycles, it plans to begin volume production in 2Q23. It also offers the Falcon development board, which includes the chip, four LPDDR4X DRAMs, connectors for automotive interfaces, a display, storage, and three video cameras.

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