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IBM Test Chip Is First at 2nm

May 25, 2021

Author: Mike Demler

IBM has manufactured the industry’s first test chip in 2nm technology. The tiny transistors implement a gate-all-around (GAA) nanosheet technology, unlike the FinFETs of current processes. IBM has been working on GAA for more than 10 years. In 2017, it proposed using the technique to mitigate scaling issues that affect FinFETs at 5nm and beyond, but integrating all the necessary process changes has delayed its adoption by foundries. The greatest obstacle has been the technology’s dependence on EUV lithography, which didn’t reach production until 2019.

Historically, semiconductor-node designations corresponded to a MOSFET’s active channel length—that is, the distance between the source and drain terminals. But the industry discarded that approach when it moved from planar transistors to FinFETs, making it difficult to compare technologies solely on the basis of their name. Process engineers now characterize new nodes on the basis of transistor-density increases; dimensions such as contacted-gate pitch and metal pitch are the main scaling parameters. Relative to a 7nm FinFET process, IBM’s 2nm technology offers 3.4x the density along with 45% faster transistors at the same power or 75% less power at the same speed. These parameters put it ahead of the projected capabilities of foundry 3nm technology, justifying the name.

The company expects the 2nm technology will be ready for partners to begin production around the end of 2024. It’s developing variants optimized for general-purpose SoCs, high-performance computing (HPC), and mobile devices. IBM previously worked with Samsung to develop 3nm GAA, but the Korean conglomerate has delayed production until 2022. In March, Intel announced an R&D partnership with IBM as part of its “IDM 2.0” strategy. It has struggled to get its 7nm node into production, but the 2nm technology could help it catch up to industry rivals.

Subscribers can view the full article in the Microprocessor Report.

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