Although the Arm v9 “Matterhorn” CPUs introduce many features that boost performance and power efficiency in client devices, they’re unable to deliver those gains without similar improvements in the interconnects that form the backbone of a multicore SoC. To support the new CPUs, Arm developed a new dynamic shared unit (DSU) and two new CoreLink interconnect products, including its first network-on-a-chip (NoC). All the new products are available for licensing.

For cache-coherent operations within the CPU cluster, the second-generation DSU-110 completely revises the DynamIQ microarchitecture. Arm says it increases L3-cache-hit bandwidth by up to 5x relative to the previous design, and it can reduce CPU leakage power by up to 75% as well. The DSU supports the new Cortex-X2, Cortex-A710, and Cortex-A510 CPUs.

The CoreLink CI-700 adds to the company’s cache-coherent-interconnect (CCI) products. It connects CPUs, deep-learning accelerators (DLAs), GPUs, and other accelerators that share data. It includes a configurable system-level cache (SLC) that supports coherent operations between the different subsystems and I/Os, and it saves power by reducing the number of DRAM transactions. The CI-700 also implements Arm v9 security features, such as the Memory Tagging Extension (MTE) that will become standard in Android phones.

For subsystems that don’t require cache-coherent operation, the company extended its network-interconnect (NIC) family by creating the CoreLink NI-700. It describes the older NIC-450 and NIC-400 as having NoC-like properties, but those products only handle packet-based point-to-point links. The NI-700 is a true NoC that implements packet-based routing, creating a new competitor for Arteris.