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Quadric’s Flexible Edge Accelerator

July 6, 2021

Author: Linley Gwennap

Startup Quadric is now sampling its first chip, a data-flow processor that can handle a range of tasks from signal processing to AI. The 256-core design consumes less than 4W and targets edge applications. The company will sell the Q16 chip on an M.2 module and also license its scalable architecture for integration in customer SoCs. A Tier One automotive supplier is already designing with the architecture. The M.2 module is now sampling, with volume production expected early next year.

Quadric’s Vortex architecture features a set of compute tiles, multiple DMA engines, and a large SRAM block, but it implements a single instruction stream that controls all the tiles. This system enables software to employ data-flow principles to optimize local-memory and compute-resource utilization. All data movement is software controlled and deterministic; the design has no caches. Using 256 tiles, the Q16 chip achieves a peak rate of four trillion operations per second (TOPS) for 8-bit integer (INT8) data. It can deliver 200 inferences per second (IPS) on the popular ResNet-50 benchmark while consuming just 2W. Using 16-bit integers, the Q16 can complete a 512-point complex FFT in 5,327 cycles.

The company offers the Vortex intellectual property (IP) in four configurations. The Q8 design has 64 tiles and can achieve 1 TOPS, making it suitable for embedded sensors. The Q16 design, as instantiated in the first chip, can handle typical edge applications. The Q32 design scales to 1,024 tiles and 16 TOPS, targeting high-end embedded and automotive-safety systems. The Q64 design can generate 64 TOPS; it could serve in an autonomous-driving system or an edge server.

Subscribers can view the full article in the Microprocessor Report.

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