The latest mobile SoCs include the debut of Arm’s Cortex-X family, creating three heterogenous CPU tiers comprising Cortex-X1, Cortex-A78, and Cortex-A55. Although this structure was supposed to bring new efficiencies to smartphone processors, our die-photo analysis shows that the initial implementations of the X1 and A78 are larger than expected, reducing performance per square millimeter. In analyzing the first 5nm processors, we also determined that the density gain from 7nm is underwhelming and far short of TSMC’s goal.

For our die analysis, we selected five chips: Apple’s A14, Huawei’s Kirin 9000, Intel’s Lakefield, Qualcomm’s Snapdragon 888, and Samsung’s Exynos 2100. Except Lakefield, all compete in the flagship-smartphone market and are optimized for performance; the Intel product instead targets thin tablet PCs with similar power constraints.

Most premium smartphone processors implement a three-tier octa-core design that includes one prime core, three mid-level cores, and four efficiency cores. Qualcomm and Samsung chose Cortex-X1 for their prime cores, but sanctions forced Huawei to select a high-frequency Cortex-A77, the smallest CPU in the group. Apple is the odd man out with its two-tier CPU subsystem: the A14 has the company’s Firestorm and Icestorm cores, which also power the M1 processor for Mac PCs.

For each processor, we gauged its maximum CPU performance, per-core area efficiency, and CPU-cluster area efficiency. To see how logic density scales from 7nm to 5nm, we compared the area of the Cortex-A55 in these processors to those in our previous analysis. Our analysis shows a density improvement of 22% to 29%, far short of TSMC’s claim of up to 44%. The original target made 5nm more of a half-node shrink, but the data shows it doesn’t even meet that mark.