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Mount Evans Puts Intel in DPU Range

September 14, 2021

Author: Bob Wheeler

Intel is often late to the networking party, but its conservative disclosure strategy has been partly to blame. After serving the smart-NIC market for years with FPGAs, the company recently disclosed architectural details of its first data-processing unit (DPU), code-named Mount Evans. Co-developed with a hyperscale cloud-service provider (CSP), the design combines a control plane and a programmable data plane to handle Ethernet speeds up to 200Gbps. Although Intel brands it as an infrastructure processing unit (IPU), the new chip fits squarely in our DPU definition, joining SoCs that include Broadcom’s Stingray, Fungible’s F1, Marvell’s Octeon, Nvidia’s BlueField, and Pensando’s Capri.

The Mount Evans SoC combines a programmable NIC subsystem and an Arm-CPU complex with 16 Neoverse N1 cores operating at up to 3.0GHz. The former comprises a PCI Express Gen4 x16 host interface, packet-processing blocks, and Ethernet ports operating at up to 200Gbps. Intel withheld process details, but we expect it builds the chip in 10nm SuperFin or in TSMC’s 7nm process.

In addition to Mount Evans, the company disclosed two new FPGA-based adapters. Oak Springs Canyon, which it brands an IPU, includes an Agilex FPGA, a Xeon D processor, 16GB of DDR4 memory for each of those two chips, a pair of 100G Ethernet ports, and a PCIe Gen4 x16 host interface. We expect general availability in 1H22, following production qualification of the unspecified Agilex device. Intel positions Oak Springs Canyon for CSPs—presumably, those not yet ready to adopt a DPU.

The other new adapter is the N6000 (Arrow Creek), positioned as a smart-NIC development platform for communications-service providers. It includes an Agilex FPGA and an Ethernet Controller E810, omitting the control-plane complexes found in Mount Evans and Oak Springs Canyon.

Subscribers can view the full article in the Microprocessor Report.

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