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Sapphire Rapids Spans Tiles

September 14, 2021

Author: Linley Gwennap

Intel’s next-generation Xeon processor, code-named Sapphire Rapids, brings major upgrades to server customers. A new platform moves to the latest DDR5 DRAM and PCIe Gen5 connections and launches the CXL interconnect for coherent accelerators. A modified CPU microarchitecture increases performance for general-purpose and AI workloads. Hardware accelerators for encryption and other features are now fully integrated. And a novel multichip approach should enable the chipmaker to close AMD’s big core-count lead. With such a long list of significant improvements, Sapphire is a game changer for Intel and its customers.

The new processor replaces Ice Lake-SP for mainstream servers and extends to the high-socket-count systems that Cooper Lake now addresses. Its Eagle Stream platform requires a motherboard upgrade for the new memory and I/O standards, which boost data rates and lane counts. The processor includes QuickAssist Technology (QAT) and other hardware accelerators previously implemented in the south-bridge chip for networking and storage processors.

Sapphire Rapids adopts an approach similar to that of AMD’s 64-core Epyc processors: spread the cores over several physical die. Instead of a single monolithic chip, the new design combines up to four identical “tiles” to achieve greater core counts. The compute tiles connect using small silicon bridges, which Intel calls an Embedded Multi-die Interconnect Bridge (EMIB), to form a single logical processor.

The processor employs Intel 7 manufacturing technology. Its new Golden Cove microarchitecture provides a 19% average gain in per-clock performance (IPC) relative to the Ice Lake generation on a suite of PC benchmarks, but the company withheld server data. The CPU includes new matrix extensions (called AMX) that greatly increase performance for CPU-based AI training and inference. In June, Intel announced that Sapphire Rapids will reach production in 1Q22, a delay from earlier plans to ship it by the end of this year.

Subscribers can view the full article in the Microprocessor Report.

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