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Qualcomm Spills Cloud AI 100 Guts

September 28, 2021

Author: Bob Wheeler

Shortly after demonstrating outstanding performance per watt in recent MLPerf Inference results, Qualcomm revealed internal-architecture details of its Cloud AI 100 accelerator at last month’s Hot Chips. The chip’s AI cores derive from smartphone designs, tracing their lineage to the Hexagon 680, which introduced vector extensions (HVX) in the Snapdragon 820. The Snapdragon 855 included the 690 generation, where Hexagon evolved into a deep-learning accelerator (DLA) by adding a tensor unit.

The Cloud AI chip extends the smartphone architecture with a larger tensor unit and more memory. Boasting 16 cores, the accelerator can perform more than 400 trillion INT8 operations per second (TOPS) and 200 trillion FP16 floating-point operations per second (flop/s) at about 70W. Even more impressive, however, is its ability to deliver 54% of its maximum performance at just 20W. The company’s expertise in low-power design helped it achieve industry-leading power efficiency for computer-vision models running on server AI accelerators.

Qualcomm has slowly revealed the Cloud AI design, starting with high-level chip features nearly one year ago. That basic outline showed a 7nm chip with 16 cores, four LPDDR4X channels, and a PCIe Gen4 x8 host interface. We now know that these cores include most of the chip’s memory and that the network-on-a-chip (NoC) connects the 16 cores, four memory controllers, and a DMA engine for the host interface. The 186GB/s NoC supports multicast and core synchronization.

Subscribers can view the full article in the Microprocessor Report.

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