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Imagination Launches RISC-V Core

July 19, 2022

Author: Bryon Moyer

Imagination Technologies has launched its first RISC-V CPU core: the RTXM-2200 for real-time applications. Although not strictly its first RISC-V implementation, it’s the first to feature the open-source instruction-set architecture (ISA) as the headliner and the first offering in the company’s new Catapult family.

The new 32-bit CPU features an in-order dual-issue core with an 11-stage pipeline. Tightly coupled memories (TCM) and memory protection provide the deterministic timing real-time applications require. Target systems include packet-processing and other networking equipment, storage controllers, base stations, and smart meters.

Internal implementations are under way using 7nm and 5nm processes. Although the company withheld performance, power, and area (PPA) metrics, it noted a 1.8GHz typical clock frequency in 7nm. Production RTL is scheduled for licensing later this quarter.

Competing against the ubiquitous Arm Cortex-R52 as well as RISC-V-based cores from Andes and SiFive, Imagination intends to take advantage of the growing RISC-V ecosystem for tools and accompanying intellectual property (IP). It plans a full range of Catapult-brand cores, starting small. This effort is the company’s second attempt at licensing CPUs following its unsuccessful MIPS experience.

Subscribers can view the full article in the Microprocessor Report.

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